top.map.qmsg

RS编码的verilog源代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "regkr RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\|regkr:regkr " "Info: Elaborating entity \"regkr\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\|regkr:regkr\"" {  } { { "KESBLOCK.V" "regkr" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 227 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "priority_encoder RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|priority_encoder:pencoder " "Info: Elaborating entity \"priority_encoder\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|priority_encoder:pencoder\"" {  } { { "KESBLOCK.V" "pencoder" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 96 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CSEEblock RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock " "Info: Elaborating entity \"CSEEblock\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\"" {  } { { "rsdecode.v" "CSEEblock" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsdecode.v" 73 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CSEEBLOCK.v(38) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(38): truncated value with size 32 to match size of target (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 CSEEBLOCK.v(46) " "Warning (10271): Verilog HDL Case Statement warning at CSEEBLOCK.v(46): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 46 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CSEEBLOCK.v(48) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(48): truncated value with size 32 to match size of target (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CSEEBLOCK.v(50) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(50): truncated value with size 32 to match size of target (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 CSEEBLOCK.v(52) " "Warning (10271): Verilog HDL Case Statement warning at CSEEBLOCK.v(52): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 52 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CSEEBLOCK.v(54) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(54): truncated value with size 32 to match size of target (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CSEEBLOCK.v(56) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(56): truncated value with size 32 to match size of target (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 56 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CSEEBLOCK.v(58) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(58): truncated value with size 32 to match size of target (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 CSEEBLOCK.v(65) " "Warning (10271): Verilog HDL Case Statement warning at CSEEBLOCK.v(65): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 65 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 CSEEBLOCK.v(69) " "Warning (10271): Verilog HDL Case Statement warning at CSEEBLOCK.v(69): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 69 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 CSEEBLOCK.v(89) " "Warning (10230): Verilog HDL assignment warning at CSEEBLOCK.v(89): truncated value with size 32 to match size of target (3)" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 89 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree0_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree0_cell:cs0_cell " "Info: Elaborating entity \"degree0_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree0_cell:cs0_cell\"" {  } { { "CSEEBLOCK.v" "cs0_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 101 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register5_wl RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree0_cell:cs0_cell\|register5_wl:register " "Info: Elaborating entity \"register5_wl\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree0_cell:cs0_cell\|register5_wl:register\"" {  } { { "CSEEBLOCK.v" "register" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 162 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree1_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree1_cell:cs1_cell " "Info: Elaborating entity \"degree1_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree1_cell:cs1_cell\"" {  } { { "CSEEBLOCK.v" "cs1_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 102 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree2_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree2_cell:cs2_cell " "Info: Elaborating entity \"degree2_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree2_cell:cs2_cell\"" {  } { { "CSEEBLOCK.v" "cs2_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 103 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree3_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree3_cell:cs3_cell " "Info: Elaborating entity \"degree3_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree3_cell:cs3_cell\"" {  } { { "CSEEBLOCK.v" "cs3_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 104 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree4_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree4_cell:cs4_cell " "Info: Elaborating entity \"degree4_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree4_cell:cs4_cell\"" {  } { { "CSEEBLOCK.v" "cs4_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 105 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree5_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree5_cell:cs5_cell " "Info: Elaborating entity \"degree5_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree5_cell:cs5_cell\"" {  } { { "CSEEBLOCK.v" "cs5_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 106 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "degree6_cell RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree6_cell:cs6_cell " "Info: Elaborating entity \"degree6_cell\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|degree6_cell:cs6_cell\"" {  } { { "CSEEBLOCK.v" "cs6_cell" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 107 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inverscomb RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|inverscomb:invers " "Info: Elaborating entity \"inverscomb\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|CSEEblock:CSEEblock\|inverscomb:invers\"" {  } { { "CSEEBLOCK.v" "invers" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 128 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MainControl RSDecoder:inst1\|rsdec:rsdec\|MainControl:controller " "Info: Elaborating entity \"MainControl\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|MainControl:controller\"" {  } { { "rsdecode.v" "controller" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsdecode.v" 78 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 DEcontroller.v(552) " "Warning (10230): Verilog HDL assignment warning at DEcontroller.v(552): truncated value with size 32 to match size of target (5)" {  } { { "DEcontroller.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/DEcontroller.v" 552 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 DEcontroller.v(560) " "Warning (10230): Verilog HDL assignment warning at DEcontroller.v(560): truncated value with size 32 to match size of target (5)" {  } { { "DEcontroller.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/DEcontroller.v" 560 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_register RSDecoder:inst1\|rsdec:rsdec\|fifo_register:fiforeg " "Info: Elaborating entity \"fifo_register\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|fifo_register:fiforeg\"" {  } { { "rsdecode.v" "fiforeg" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsdecode.v" 84 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}