top.map.qmsg

RS编码的verilog源代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register5_wlh RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_0:cell_0\|register5_wlh:register5bit " "Info: Elaborating entity \"register5_wlh\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_0:cell_0\|register5_wlh:register5bit\"" {  } { { "SCBLOCK.V" "register5bit" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 103 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gfadder RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_0:cell_0\|gfadder:adder " "Info: Elaborating entity \"gfadder\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_0:cell_0\|gfadder:adder\"" {  } { { "SCBLOCK.V" "adder" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 104 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_1 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_1:cell_1 " "Info: Elaborating entity \"syndcell_1\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_1:cell_1\"" {  } { { "SCBLOCK.V" "cell_1" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 67 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_2 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_2:cell_2 " "Info: Elaborating entity \"syndcell_2\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_2:cell_2\"" {  } { { "SCBLOCK.V" "cell_2" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 68 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_3 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_3:cell_3 " "Info: Elaborating entity \"syndcell_3\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_3:cell_3\"" {  } { { "SCBLOCK.V" "cell_3" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 69 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_4 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_4:cell_4 " "Info: Elaborating entity \"syndcell_4\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_4:cell_4\"" {  } { { "SCBLOCK.V" "cell_4" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_5 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_5:cell_5 " "Info: Elaborating entity \"syndcell_5\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_5:cell_5\"" {  } { { "SCBLOCK.V" "cell_5" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_6 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_6:cell_6 " "Info: Elaborating entity \"syndcell_6\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_6:cell_6\"" {  } { { "SCBLOCK.V" "cell_6" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_7 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_7:cell_7 " "Info: Elaborating entity \"syndcell_7\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_7:cell_7\"" {  } { { "SCBLOCK.V" "cell_7" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 73 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_8 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_8:cell_8 " "Info: Elaborating entity \"syndcell_8\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_8:cell_8\"" {  } { { "SCBLOCK.V" "cell_8" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 74 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_9 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_9:cell_9 " "Info: Elaborating entity \"syndcell_9\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_9:cell_9\"" {  } { { "SCBLOCK.V" "cell_9" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_10 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_10:cell_10 " "Info: Elaborating entity \"syndcell_10\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_10:cell_10\"" {  } { { "SCBLOCK.V" "cell_10" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 76 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_11 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_11:cell_11 " "Info: Elaborating entity \"syndcell_11\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_11:cell_11\"" {  } { { "SCBLOCK.V" "cell_11" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KES_block RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock " "Info: Elaborating entity \"KES_block\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\"" {  } { { "rsdecode.v" "KESblock" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsdecode.v" 68 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PE RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0 " "Info: Elaborating entity \"PE\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\"" {  } { { "KESBLOCK.V" "PE0" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 26 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcpmult RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\|lcpmult:multiplier1 " "Info: Elaborating entity \"lcpmult\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\|lcpmult:multiplier1\"" {  } { { "KESBLOCK.V" "multiplier1" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 341 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_pe RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\|register_pe:reg1 " "Info: Elaborating entity \"register_pe\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\|register_pe:reg1\"" {  } { { "KESBLOCK.V" "reg1" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 343 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux2_to_1 RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\|mux2_to_1:multiplexer " "Info: Elaborating entity \"mux2_to_1\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE:PE0\|mux2_to_1:multiplexer\"" {  } { { "KESBLOCK.V" "multiplexer" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 345 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 common_modules.v(12) " "Warning (10271): Verilog HDL Case Statement warning at common_modules.v(12): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 12 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 common_modules.v(13) " "Warning (10271): Verilog HDL Case Statement warning at common_modules.v(13): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 13 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PE_12 RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE_12:PE12 " "Info: Elaborating entity \"PE_12\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE_12:PE12\"" {  } { { "KESBLOCK.V" "PE12" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 50 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PE_18 RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE_18:PE18 " "Info: Elaborating entity \"PE_18\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|PE_18:PE18\"" {  } { { "KESBLOCK.V" "PE18" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol " "Info: Elaborating entity \"control\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\"" {  } { { "KESBLOCK.V" "mcontrol" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 64 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "st5 KESBLOCK.V(122) " "Warning (10036): Verilog HDL or VHDL warning at KESBLOCK.V(122): object \"st5\" assigned a value but never read" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 122 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 KESBLOCK.V(129) " "Warning (10230): Verilog HDL assignment warning at KESBLOCK.V(129): truncated value with size 32 to match size of target (4)" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fulladder RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\|fulladder:adder " "Info: Elaborating entity \"fulladder\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\|fulladder:adder\"" {  } { { "KESBLOCK.V" "adder" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 225 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "regamma RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\|regamma:reggamma " "Info: Elaborating entity \"regamma\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|KES_block:KESblock\|control:mcontrol\|regamma:reggamma\"" {  } { { "KESBLOCK.V" "reggamma" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 226 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}