top.map.qmsg

RS编码的verilog源代码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RSEncoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RSEncoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 RSEncoder " "Info: Found entity 1: RSEncoder" {  } { { "RSEncoder.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSEncoder.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RSDecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RSDecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 RSDecoder " "Info: Found entity 1: RSDecoder" {  } { { "RSDecoder.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 Clock " "Info: Found entity 1: Clock" {  } { { "Clock.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/Clock.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file rs.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 rs " "Info: Found entity 1: rs" {  } { { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "error.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file error.v" { { "Info" "ISGN_ENTITY_NAME" "1 error " "Info: Found entity 1: error" {  } { { "error.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/error.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rs " "Info: Elaborating entity \"rs\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RSDecoder RSDecoder:inst1 " "Info: Elaborating entity \"RSDecoder\" for hierarchy \"RSDecoder:inst1\"" {  } { { "rs.bdf" "inst1" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 88 944 1152 408 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide5 RSDecoder:inst1\|divide5:dividea " "Info: Elaborating entity \"divide5\" for hierarchy \"RSDecoder:inst1\|divide5:dividea\"" {  } { { "RSDecoder.v" "dividea" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 26 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 frequency divider.v(18) " "Warning (10230): Verilog HDL assignment warning at frequency divider.v(18): truncated value with size 32 to match size of target (3)" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bit2Dec RSDecoder:inst1\|Bit2Dec:Bit2Dec " "Info: Elaborating entity \"Bit2Dec\" for hierarchy \"RSDecoder:inst1\|Bit2Dec:Bit2Dec\"" {  } { { "RSDecoder.v" "Bit2Dec" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 30 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clkout serial_paralled_conversion.v(49) " "Info (10035): Verilog HDL or VHDL information at serial_paralled_conversion.v(49): object \"clkout\" declared but not used" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 49 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 serial_paralled_conversion.v(90) " "Warning (10230): Verilog HDL assignment warning at serial_paralled_conversion.v(90): truncated value with size 32 to match size of target (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "before_decode RSDecoder:inst1\|before_decode:before_decode " "Info: Elaborating entity \"before_decode\" for hierarchy \"RSDecoder:inst1\|before_decode:before_decode\"" {  } { { "RSDecoder.v" "before_decode" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 33 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "start RAM_fifo_all.v(196) " "Info (10035): Verilog HDL or VHDL information at RAM_fifo_all.v(196): object \"start\" declared but not used" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 196 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 RAM_fifo_all.v(233) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(233): truncated value with size 32 to match size of target (5)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 233 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 RAM_fifo_all.v(235) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(235): truncated value with size 32 to match size of target (5)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 235 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 RAM_fifo_all.v(262) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(262): truncated value with size 32 to match size of target (6)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 262 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 RAM_fifo_all.v(267) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(267): truncated value with size 32 to match size of target (6)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 267 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 5 RAM_fifo_all.v(268) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(268): truncated value with size 6 to match size of target (5)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 268 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dp0 RSDecoder:inst1\|lpm_ram_dp0:ram1 " "Info: Elaborating entity \"lpm_ram_dp0\" for hierarchy \"RSDecoder:inst1\|lpm_ram_dp0:ram1\"" {  } { { "RSDecoder.v" "ram1" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\"" {  } { { "RAM.v" "altsyncram_component" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM.v" 29 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lva1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lva1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lva1 " "Info: Found entity 1: altsyncram_lva1" {  } { { "db/altsyncram_lva1.tdf" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/altsyncram_lva1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lva1 RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\|altsyncram_lva1:auto_generated " "Info: Elaborating entity \"altsyncram_lva1\" for hierarchy \"RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\|altsyncram_lva1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rsdec RSDecoder:inst1\|rsdec:rsdec " "Info: Elaborating entity \"rsdec\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\"" {  } { { "RSDecoder.v" "rsdec" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SCblock RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock " "Info: Elaborating entity \"SCblock\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\"" {  } { { "rsdecode.v" "SCblock" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsdecode.v" 63 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "syndcell_0 RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_0:cell_0 " "Info: Elaborating entity \"syndcell_0\" for hierarchy \"RSDecoder:inst1\|rsdec:rsdec\|SCblock:SCblock\|syndcell_0:cell_0\"" {  } { { "SCBLOCK.V" "cell_0" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 66 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}