top.map.qmsg

RS编码的verilog源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 13 09:42:13 2007 " "Info: Processing started: Wed Jun 13 09:42:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RS_encode_and_decode -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RS_encode_and_decode -c top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/pll.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rsencode.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file rsencode.v" { { "Info" "ISGN_ENTITY_NAME" "1 rsenc " "Info: Found entity 1: rsenc" {  } { { "rsencode.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsencode.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 mul " "Info: Found entity 2: mul" {  } { { "rsencode.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsencode.v" 79 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rsdecode.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rsdecode.v" { { "Info" "ISGN_ENTITY_NAME" "1 rsdec " "Info: Found entity 1: rsdec" {  } { { "rsdecode.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rsdecode.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_fifo_all.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file RAM_fifo_all.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_encode " "Info: Found entity 1: fifo_encode" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 fifo_decode " "Info: Found entity 2: fifo_decode" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 90 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 before_decode " "Info: Found entity 3: before_decode" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 193 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RAM.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dp0 " "Info: Found entity 1: lpm_ram_dp0" {  } { { "RAM.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "source_nrz.v(9) " "Warning (10268): Verilog HDL information at source_nrz.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "source_nrz.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/source_nrz.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source_nrz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file source_nrz.v" { { "Info" "ISGN_ENTITY_NAME" "1 nrz " "Info: Found entity 1: nrz" {  } { { "source_nrz.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/source_nrz.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SCBLOCK.V(47) " "Warning (10268): Verilog HDL information at SCBLOCK.V(47): Always Construct contains both blocking and non-blocking assignments" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 47 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SCBLOCK.V 13 13 " "Info: Found 13 design units, including 13 entities, in source file SCBLOCK.V" { { "Info" "ISGN_ENTITY_NAME" "1 SCblock " "Info: Found entity 1: SCblock" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 syndcell_0 " "Info: Found entity 2: syndcell_0" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 85 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 syndcell_1 " "Info: Found entity 3: syndcell_1" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 111 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 syndcell_2 " "Info: Found entity 4: syndcell_2" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 136 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 syndcell_3 " "Info: Found entity 5: syndcell_3" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 161 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 syndcell_4 " "Info: Found entity 6: syndcell_4" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 186 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 syndcell_5 " "Info: Found entity 7: syndcell_5" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 211 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 syndcell_6 " "Info: Found entity 8: syndcell_6" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 235 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 syndcell_7 " "Info: Found entity 9: syndcell_7" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 260 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 syndcell_8 " "Info: Found entity 10: syndcell_8" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 285 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 syndcell_9 " "Info: Found entity 11: syndcell_9" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 310 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 syndcell_10 " "Info: Found entity 12: syndcell_10" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 335 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 syndcell_11 " "Info: Found entity 13: syndcell_11" {  } { { "SCBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/SCBLOCK.V" 360 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "common_modules.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file common_modules.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux2_to_1 " "Info: Found entity 1: mux2_to_1" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 register5_wlh " "Info: Found entity 2: register5_wlh" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 register5_wl " "Info: Found entity 3: register5_wl" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 gfadder " "Info: Found entity 4: gfadder" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 62 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 lcpmult " "Info: Found entity 5: lcpmult" {  } { { "common_modules.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/common_modules.v" 76 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CSEEBLOCK.v 9 9 " "Info: Found 9 design units, including 9 entities, in source file CSEEBLOCK.v" { { "Info" "ISGN_ENTITY_NAME" "1 CSEEblock " "Info: Found entity 1: CSEEblock" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 degree0_cell " "Info: Found entity 2: degree0_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 155 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 degree1_cell " "Info: Found entity 3: degree1_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 171 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 degree2_cell " "Info: Found entity 4: degree2_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 197 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 degree3_cell " "Info: Found entity 5: degree3_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 226 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 degree4_cell " "Info: Found entity 6: degree4_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 251 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 degree5_cell " "Info: Found entity 7: degree5_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 277 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 degree6_cell " "Info: Found entity 8: degree6_cell" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 303 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 inverscomb " "Info: Found entity 9: inverscomb" {  } { { "CSEEBLOCK.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/CSEEBLOCK.v" 334 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DEcontroller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DEcontroller.v" { { "Info" "ISGN_ENTITY_NAME" "1 MainControl " "Info: Found entity 1: MainControl" {  } { { "DEcontroller.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/DEcontroller.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo_register.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fifo_register.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_register " "Info: Found entity 1: fifo_register" {  } { { "fifo_register.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/fifo_register.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "KESBLOCK.V 10 10 " "Info: Found 10 design units, including 10 entities, in source file KESBLOCK.V" { { "Info" "ISGN_ENTITY_NAME" "1 KES_block " "Info: Found entity 1: KES_block" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 control " "Info: Found entity 2: control" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 104 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 fulladder " "Info: Found entity 3: fulladder" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 235 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 regamma " "Info: Found entity 4: regamma" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 259 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 regkr " "Info: Found entity 5: regkr" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 284 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 priority_encoder " "Info: Found entity 6: priority_encoder" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 310 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 PE " "Info: Found entity 7: PE" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 330 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 PE_12 " "Info: Found entity 8: PE_12" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 358 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 PE_18 " "Info: Found entity 9: PE_18" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 390 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 register_pe " "Info: Found entity 10: register_pe" {  } { { "KESBLOCK.V" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/KESBLOCK.V" 415 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "wordstart1 top.v(33) " "Warning (10236): Verilog HDL net warning at top.v(33): created undeclared net \"wordstart1\"" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 33 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "wordstart2 top.v(33) " "Warning (10236): Verilog HDL net warning at top.v(33): created undeclared net \"wordstart2\"" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 33 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ramout top.v(33) " "Warning (10236): Verilog HDL net warning at top.v(33): created undeclared net \"ramout\"" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 33 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "rdaddress top.v(33) " "Warning (10236): Verilog HDL net warning at top.v(33): created undeclared net \"rdaddress\"" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 33 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "wraddress top.v(33) " "Warning (10236): Verilog HDL net warning at top.v(33): created undeclared net \"wraddress\"" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 33 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 mydff " "Info: Found entity 2: mydff" {  } { { "top.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.v" 48 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "serial_paralled_conversion.v(17) " "Warning (10268): Verilog HDL information at serial_paralled_conversion.v(17): Always Construct contains both blocking and non-blocking assignments" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 17 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "serial_paralled_conversion.v(62) " "Warning (10268): Verilog HDL information at serial_paralled_conversion.v(62): Always Construct contains both blocking and non-blocking assignments" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 62 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial_paralled_conversion.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file serial_paralled_conversion.v" { { "Info" "ISGN_ENTITY_NAME" "1 Dec2Bit " "Info: Found entity 1: Dec2Bit" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 Bit2Dec " "Info: Found entity 2: Bit2Dec" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 48 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frequency divider.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file frequency divider.v" { { "Info" "ISGN_ENTITY_NAME" "1 divide5 " "Info: Found entity 1: divide5" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 divide3 " "Info: Found entity 2: divide3" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}