top.fit.qmsg

RS编码的verilog源代码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:13 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:13" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:29 " "Info: Fitter placement operations ending: elapsed time is 00:00:29" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.933 ns register register " "Info: Estimated most critical path is register to register delay of 2.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RSEncoder:inst\|fifo_encode:B\|temp\[0\] 1 REG LAB_X11_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y14; Fanout = 4; REG Node = 'RSEncoder:inst\|fifo_encode:B\|temp\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.590 ns) 0.740 ns RSEncoder:inst\|fifo_encode:B\|always2~296 2 COMB LAB_X11_Y14 1 " "Info: 2: + IC(0.150 ns) + CELL(0.590 ns) = 0.740 ns; Loc. = LAB_X11_Y14; Fanout = 1; COMB Node = 'RSEncoder:inst\|fifo_encode:B\|always2~296'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.740 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.442 ns) 1.630 ns RSEncoder:inst\|fifo_encode:B\|always2~0 3 COMB LAB_X12_Y14 8 " "Info: 3: + IC(0.448 ns) + CELL(0.442 ns) = 1.630 ns; Loc. = LAB_X12_Y14; Fanout = 8; COMB Node = 'RSEncoder:inst\|fifo_encode:B\|always2~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.890 ns" { RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.867 ns) 2.933 ns RSEncoder:inst\|fifo_encode:B\|rdclocken 4 REG LAB_X12_Y14 30 " "Info: 4: + IC(0.436 ns) + CELL(0.867 ns) = 2.933 ns; Loc. = LAB_X12_Y14; Fanout = 30; REG Node = 'RSEncoder:inst\|fifo_encode:B\|rdclocken'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.303 ns" { RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns ( 64.75 % ) " "Info: Total cell delay = 1.899 ns ( 64.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.034 ns ( 35.25 % ) " "Info: Total interconnect delay = 1.034 ns ( 35.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "2.933 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 17 " "Info: Average interconnect usage is 7% of the available device resources. Peak interconnect usage is 17%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:17 " "Info: Fitter routing operations ending: elapsed time is 00:00:17" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress~10 " "Info: Node RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress~10 uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear RSDecoder:inst1\|fifo_decode:fifo_decode\|temp1\[1\] " "Info: Port clear -- assigned as a global for destination node RSDecoder:inst1\|fifo_decode:fifo_decode\|temp1\[1\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|temp1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|fifo_decode:fifo_decode\|temp1\[1\]" } } } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 114 -1 0 } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|temp1[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress\[2\] " "Info: Port clear -- assigned as a global for destination node RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress\[2\]" } } } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 114 -1 0 } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress\[1\] " "Info: Port clear -- assigned as a global for destination node RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress\[1\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress\[1\]" } } } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 114 -1 0 } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|wraddress[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear RSDecoder:inst1\|fifo_decode:fifo_decode\|temp1\[2\] " "Info: Port clear -- assigned as a global for destination node RSDecoder:inst1\|fifo_decode:fifo_decode\|temp1\[2\] -- routed using non-global resources" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|temp1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|fifo_decode:fifo_decode\|temp1\[2\]" } } } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 114 -1 0 } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|temp1[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|wraddress~10 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|fifo_decode:fifo_decode\|wraddress~10" } } } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 95 -1 0 } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { RSDecoder:inst1|fifo_decode:fifo_decode|wraddress~10 } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 13 09:44:57 2007 " "Info: Processing ended: Wed Jun 13 09:44:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:24 " "Info: Elapsed time: 00:01:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}