top.fit.qmsg

RS编码的verilog源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 13 09:43:34 2007 " "Info: Processing started: Wed Jun 13 09:43:34 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RS_encode_and_decode -c top " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RS_encode_and_decode -c top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "top EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"top\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 25 46 0 0 " "Info: Implementing clock multiplication of 25, clock division of 46, and phase shift of 0 degrees (0 ps) for Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "pll.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/pll.v" 56 -1 0 } } { "Clock.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/Clock.v" 7 -1 0 } } { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 88 104 200 184 "inst3" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "3 11 " "Info: No exact pin location assignment(s) for 3 pins of 11 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "error " "Info: Pin error not assigned to an exact location on the device" {  } { { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 424 704 880 440 "error" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "error" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { error } "NODE_NAME" } "" } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { error } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adderror " "Info: Pin adderror not assigned to an exact location on the device" {  } { { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 448 952 1128 464 "adderror" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "adderror" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { adderror } "NODE_NAME" } "" } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { adderror } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "be_adderror " "Info: Pin be_adderror not assigned to an exact location on the device" {  } { { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 488 576 752 504 "be_adderror" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "be_adderror" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { be_adderror } "NODE_NAME" } "" } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { be_adderror } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "clk " "Info: Promoted signal \"clk\" to use global clock" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } { 0 "clk" } } } } { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 112 -144 24 128 "clk" "" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { clk } "NODE_NAME" } "" } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0" } { 0 "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0" } } } } { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 88 104 200 184 "inst3" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/top.fld" "" "" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RSDecoder:inst1\|divide5:dividec\|clk_out Global clock " "Info: Automatically promoted signal \"RSDecoder:inst1\|divide5:dividec\|clk_out\" to use Global clock" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RSEncoder:inst\|divide5:divideb\|clk_out Global clock " "Info: Automatically promoted signal \"RSEncoder:inst\|divide5:divideb\|clk_out\" to use Global clock" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}