top.qsf

RS编码的verilog源代码

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY rs
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:14:12  MAY 15, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
set_global_assignment -name VECTOR_INPUT_SOURCE "D:\\6.11开始\\RS_19_31_EP1C6Q240_TEST1\\adderror_test.vwf"
set_global_assignment -name VERILOG_FILE pll.v
set_global_assignment -name VERILOG_FILE rsencode.v
set_global_assignment -name VERILOG_FILE rsdecode.v
set_global_assignment -name VERILOG_FILE RAM_fifo_all.v
set_global_assignment -name VERILOG_FILE RAM.v
set_global_assignment -name VERILOG_FILE source_nrz.v
set_global_assignment -name VERILOG_FILE SCBLOCK.V
set_global_assignment -name VERILOG_FILE common_modules.v
set_global_assignment -name VERILOG_FILE CSEEBLOCK.v
set_global_assignment -name VERILOG_FILE DEcontroller.v
set_global_assignment -name VERILOG_FILE fifo_register.v
set_global_assignment -name VERILOG_FILE KESBLOCK.V
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VECTOR_WAVEFORM_FILE encode.vwf
set_global_assignment -name VERILOG_FILE serial_paralled_conversion.v
set_global_assignment -name VERILOG_FILE "frequency divider.v"
set_global_assignment -name VERILOG_FILE RSEncoder.v
set_global_assignment -name VERILOG_FILE RSDecoder.v
set_global_assignment -name VERILOG_FILE Clock.v
set_global_assignment -name BDF_FILE rs.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE rs.vwf
set_location_assignment PIN_82 -to bitout
set_location_assignment PIN_153 -to clk
set_location_assignment PIN_78 -to reset
set_location_assignment PIN_83 -to bitoutstart
set_location_assignment PIN_84 -to errfound
set_location_assignment PIN_85 -to fail
set_location_assignment PIN_79 -to bitin
set_location_assignment PIN_87 -to bitinstart
set_location_assignment PIN_24 -to ~nCSO~
set_location_assignment PIN_37 -to ~ASDO~
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to reset
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to reset
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to clk
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to clk
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to bitout
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to bitout
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to bitoutstart
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to bitoutstart
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to errfound
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to errfound
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to fail
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to fail
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to bitin
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to bitin
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER ON -to bitinstart
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to bitinstart
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE error.v
set_global_assignment -name VECTOR_WAVEFORM_FILE adderror_test.vwf