frequency divider.v

RS编码的verilog源代码

module divide5(clk_in,rst,clk_out);
   input clk_in;
   input rst;
   output clk_out;
   reg clk_out;
   reg clk_temp1;
   reg clk_temp2;
   reg[2:0] counter;
   always @(posedge clk_in)
     begin
       if(!rst)
         begin
           counter<=0;
           clk_temp1<=0;
          end
        else
         begin   
           counter<=counter+1;
            if(counter==2)
             clk_temp1<=!clk_temp1;
            else if(counter==4)
              begin
               clk_temp1<=!clk_temp1;
               counter<=0;
              end
            end
          end
always @(negedge clk_in)
begin
   if(!rst)
     clk_temp2<=0;
   else 
     clk_temp2<=clk_temp1;
  end
always @(clk_temp1 or clk_temp2)
clk_out=clk_temp1|clk_temp2;
endmodule


module divide3(clk_in,rst,clk_out);
   input clk_in;
   input rst;
   output clk_out;
   reg clk_out;
   reg clk_temp1;
   reg clk_temp2;
   reg[2:0] counter;
   always @(posedge clk_in)
     begin
       if(!rst)
         begin
           counter<=0;
           clk_temp1<=0;
          end
        else
         begin   
           counter<=counter+1;
            if(counter==1)
             clk_temp1<=!clk_temp1;
            else if(counter==2)
              begin
               clk_temp1<=!clk_temp1;
               counter<=0;
              end
            end
          end
always @(negedge clk_in)
begin
   if(!rst)
     clk_temp2<=0;
   else 
     clk_temp2<=clk_temp1;
  end
always @(clk_temp1 or clk_temp2)
clk_out=clk_temp1|clk_temp2;
endmodule