top.map.smsg

RS编码的verilog源代码

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Jun 12 11:09:53 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RS_encode_and_decode -c top
Info: Found 1 design units, including 1 entities, in source file pll.v
    Info: Found entity 1: pll
Info: Found 2 design units, including 2 entities, in source file rsencode.v
    Info: Found entity 1: rsenc
    Info: Found entity 2: mul
Info: Found 1 design units, including 1 entities, in source file rsdecode.v
    Info: Found entity 1: rsdec
Info: Found 3 design units, including 3 entities, in source file RAM_fifo_all.v
    Info: Found entity 1: fifo_encode
    Info: Found entity 2: fifo_decode
    Info: Found entity 3: before_decode
Info: Found 1 design units, including 1 entities, in source file RAM.v
    Info: Found entity 1: lpm_ram_dp0
Info: Found 1 design units, including 1 entities, in source file source_nrz.v
    Info: Found entity 1: nrz
Info: Found 13 design units, including 13 entities, in source file SCBLOCK.V
    Info: Found entity 1: SCblock
    Info: Found entity 2: syndcell_0
    Info: Found entity 3: syndcell_1
    Info: Found entity 4: syndcell_2
    Info: Found entity 5: syndcell_3
    Info: Found entity 6: syndcell_4
    Info: Found entity 7: syndcell_5
    Info: Found entity 8: syndcell_6
    Info: Found entity 9: syndcell_7
    Info: Found entity 10: syndcell_8
    Info: Found entity 11: syndcell_9
    Info: Found entity 12: syndcell_10
    Info: Found entity 13: syndcell_11
Info: Found 5 design units, including 5 entities, in source file common_modules.v
    Info: Found entity 1: mux2_to_1
    Info: Found entity 2: register5_wlh
    Info: Found entity 3: register5_wl
    Info: Found entity 4: gfadder
    Info: Found entity 5: lcpmult
Info: Found 9 design units, including 9 entities, in source file CSEEBLOCK.v
    Info: Found entity 1: CSEEblock
    Info: Found entity 2: degree0_cell
    Info: Found entity 3: degree1_cell
    Info: Found entity 4: degree2_cell
    Info: Found entity 5: degree3_cell
    Info: Found entity 6: degree4_cell
    Info: Found entity 7: degree5_cell
    Info: Found entity 8: degree6_cell
    Info: Found entity 9: inverscomb
Info: Found 1 design units, including 1 entities, in source file DEcontroller.v
    Info: Found entity 1: MainControl
Info: Found 1 design units, including 1 entities, in source file fifo_register.v
    Info: Found entity 1: fifo_register
Info: Found 10 design units, including 10 entities, in source file KESBLOCK.V
    Info: Found entity 1: KES_block
    Info: Found entity 2: control
    Info: Found entity 3: fulladder
    Info: Found entity 4: regamma
    Info: Found entity 5: regkr
    Info: Found entity 6: priority_encoder
    Info: Found entity 7: PE
    Info: Found entity 8: PE_12
    Info: Found entity 9: PE_18
    Info: Found entity 10: register_pe
Info: Found 2 design units, including 2 entities, in source file top.v
    Info: Found entity 1: top
    Info: Found entity 2: mydff
Info: Found 2 design units, including 2 entities, in source file serial_paralled_conversion.v
    Info: Found entity 1: Dec2Bit
    Info: Found entity 2: Bit2Dec
Info: Found 2 design units, including 2 entities, in source file frequency divider.v
    Info: Found entity 1: divide5
    Info: Found entity 2: divide3
Info: Found 1 design units, including 1 entities, in source file RSEncoder.v
    Info: Found entity 1: RSEncoder
Info: Found 1 design units, including 1 entities, in source file RSDecoder.v
    Info: Found entity 1: RSDecoder
Info: Found 1 design units, including 1 entities, in source file Clock.v
    Info: Found entity 1: Clock
Info: Found 1 design units, including 1 entities, in source file rs.bdf
    Info: Found entity 1: rs
Info: Elaborating entity "rs" for the top level hierarchy
Info: Elaborating entity "RSDecoder" for hierarchy "RSDecoder:inst1"
Info: Elaborating entity "divide5" for hierarchy "RSDecoder:inst1|divide5:dividea"
Warning (10230): Verilog HDL assignment warning at frequency divider.v(18): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "Bit2Dec" for hierarchy "RSDecoder:inst1|Bit2Dec:Bit2Dec"
Warning (10230): Verilog HDL assignment warning at serial_paralled_conversion.v(90): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "before_decode" for hierarchy "RSDecoder:inst1|before_decode:before_decode"
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(233): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(235): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(262): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(267): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(268): truncated value with size 6 to match size of target (5)
Info: Elaborating entity "lpm_ram_dp0" for hierarchy "RSDecoder:inst1|lpm_ram_dp0:ram1"
Info: Found 1 design units, including 1 entities, in source file f:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_52i1.tdf
    Info: Found entity 1: altsyncram_52i1
Info: Elaborating entity "altsyncram_52i1" for hierarchy "RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_52i1:auto_generated"
Info: Elaborating entity "rsdec" for hierarchy "RSDecoder:inst1|rsdec:rsdec"
Info: Elaborating entity "SCblock" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock"
Info: Elaborating entity "syndcell_0" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0"
Info: Elaborating entity "register5_wlh" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit"
Info: Elaborating entity "gfadder" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|gfadder:adder"
Info: Elaborating entity "syndcell_1" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1"
Info: Elaborating entity "syndcell_2" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2"
Info: Elaborating entity "syndcell_3" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3"
Info: Elaborating entity "syndcell_4" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4"
Info: Elaborating entity "syndcell_5" for hierarchy "RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5"