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来自「RS编码的verilog源代码」· SUMMARY 代码 · 共 87 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.786 ns
From           : reset
To             : RSDecoder:inst1|Bit2Dec:Bit2Dec|c5
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.003 ns
From           : RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_11
To             : fail
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.442 ns
From           : reset
To             : nrz:inst2|c1
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0'
Slack          : -9.142 ns
Required Time  : 36.73 MHz ( period = 27.224 ns )
Actual Time    : N/A
From           : RSEncoder:inst|fifo_encode:B|temp[0]
To             : RSEncoder:inst|fifo_encode:B|rdclocken
From Clock     : clk
To Clock       : Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0
Failed Paths   : 48

Type           : Clock Setup: 'clk'
Slack          : -2.790 ns
Required Time  : 67.59 MHz ( period = 14.796 ns )
Actual Time    : 49.08 MHz ( period = 20.376 ns )
From           : RSDecoder:inst1|Dec2Bit:Dec2Bit|enable
To             : RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 163

Type           : Clock Hold: 'clk'
Slack          : -3.579 ns
Required Time  : 67.59 MHz ( period = 14.796 ns )
Actual Time    : N/A
From           : RSEncoder:inst|Bit2Dec:A|out[0]
To             : RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ram_block1a3~porta_datain_reg4
From Clock     : clk
To Clock       : clk
Failed Paths   : 23

Type           : Clock Hold: 'Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0'
Slack          : -3.147 ns
Required Time  : 36.73 MHz ( period = 27.224 ns )
Actual Time    : N/A
From           : RSDecoder:inst1|Bit2Dec:Bit2Dec|out[4]
To             : RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ram_block1a3~porta_datain_reg4
From Clock     : Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0
To Clock       : Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0
Failed Paths   : 16

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 250

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