top.fit.eqn

RS编码的verilog源代码

--operation mode is arithmetic

F1L7_cout_0 = F1_cnt[0];
F1L7 = CARRY(F1L7_cout_0);

--F1L8 is error:inst6|cnt[0]~81COUT1_95 at LC_X10_Y14_N0
--operation mode is arithmetic

F1L8_cout_1 = F1_cnt[0];
F1L8 = CARRY(F1L8_cout_1);


--F1_cnt[3] is error:inst6|cnt[3] at LC_X10_Y14_N3
--operation mode is arithmetic

F1_cnt[3]_lut_out = F1_cnt[3] $ F1L13;
F1_cnt[3] = DFFEAS(F1_cnt[3]_lut_out, GLOBAL(MC1__clk0), VCC, , , , , , );

--F1L16 is error:inst6|cnt[3]~85 at LC_X10_Y14_N3
--operation mode is arithmetic

F1L16_cout_0 = !F1L13 # !F1_cnt[3];
F1L16 = CARRY(F1L16_cout_0);

--F1L17 is error:inst6|cnt[3]~85COUT1_100 at LC_X10_Y14_N3
--operation mode is arithmetic

F1L17_cout_1 = !F1L14 # !F1_cnt[3];
F1L17 = CARRY(F1L17_cout_1);


--F1L2 is error:inst6|always0~618 at LC_X10_Y13_N5
--operation mode is normal

F1L2 = F1_cnt[3] & (F1_cnt[0] $ F1_cnt[7]);


--F1L3 is error:inst6|always0~619 at LC_X10_Y14_N8
--operation mode is normal

F1L3 = !F1_cnt[5] & (F1_cnt[4] & !F1_cnt[2] & !F1_cnt[7] # !F1_cnt[4] & (F1_cnt[7]));


--F1L4 is error:inst6|always0~620 at LC_X10_Y13_N2
--operation mode is normal

F1L4 = F1L2 & (F1L3 $ F1_cnt[1]);


--MC1__clk0 is Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 at PLL_2
MC1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GND), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--P3_q_b[3] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3] at M4K_X17_Y14
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 5, Port B Depth: 32, Port B Width: 5
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P3_q_b[3]_PORT_A_data_in = BUS(G2_out[3], G2_out[4], G2_out[2], G2_out[1], G2_out[0]);
P3_q_b[3]_PORT_A_data_in_reg = DFFE(P3_q_b[3]_PORT_A_data_in, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[3]_PORT_A_address_reg = DFFE(P3_q_b[3]_PORT_A_address, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[3]_PORT_B_address_reg = DFFE(P3_q_b[3]_PORT_B_address, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[3]_PORT_A_write_enable_reg = DFFE(P3_q_b[3]_PORT_A_write_enable, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_read_enable = VCC;
P3_q_b[3]_PORT_B_read_enable_reg = DFFE(P3_q_b[3]_PORT_B_read_enable, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_clock_0 = GLOBAL(M1_clk_out);
P3_q_b[3]_clock_1 = GLOBAL(M5_clk_out);
P3_q_b[3]_clock_enable_0 = H1_wrclocken;
P3_q_b[3]_clock_enable_1 = H1_rdclocken;
P3_q_b[3]_PORT_B_data_out = MEMORY(P3_q_b[3]_PORT_A_data_in_reg, , P3_q_b[3]_PORT_A_address_reg, P3_q_b[3]_PORT_B_address_reg, P3_q_b[3]_PORT_A_write_enable_reg, P3_q_b[3]_PORT_B_read_enable_reg, , , P3_q_b[3]_clock_0, P3_q_b[3]_clock_1, P3_q_b[3]_clock_enable_0, P3_q_b[3]_clock_enable_1, , );
P3_q_b[3]_PORT_B_data_out_reg = DFFE(P3_q_b[3]_PORT_B_data_out, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3] = P3_q_b[3]_PORT_B_data_out_reg[0];

--P3_q_b[0] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[0] at M4K_X17_Y14
P3_q_b[3]_PORT_A_data_in = BUS(G2_out[3], G2_out[4], G2_out[2], G2_out[1], G2_out[0]);
P3_q_b[3]_PORT_A_data_in_reg = DFFE(P3_q_b[3]_PORT_A_data_in, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[3]_PORT_A_address_reg = DFFE(P3_q_b[3]_PORT_A_address, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[3]_PORT_B_address_reg = DFFE(P3_q_b[3]_PORT_B_address, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[3]_PORT_A_write_enable_reg = DFFE(P3_q_b[3]_PORT_A_write_enable, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_read_enable = VCC;
P3_q_b[3]_PORT_B_read_enable_reg = DFFE(P3_q_b[3]_PORT_B_read_enable, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_clock_0 = GLOBAL(M1_clk_out);
P3_q_b[3]_clock_1 = GLOBAL(M5_clk_out);
P3_q_b[3]_clock_enable_0 = H1_wrclocken;
P3_q_b[3]_clock_enable_1 = H1_rdclocken;
P3_q_b[3]_PORT_B_data_out = MEMORY(P3_q_b[3]_PORT_A_data_in_reg, , P3_q_b[3]_PORT_A_address_reg, P3_q_b[3]_PORT_B_address_reg, P3_q_b[3]_PORT_A_write_enable_reg, P3_q_b[3]_PORT_B_read_enable_reg, , , P3_q_b[3]_clock_0, P3_q_b[3]_clock_1, P3_q_b[3]_clock_enable_0, P3_q_b[3]_clock_enable_1, , );
P3_q_b[3]_PORT_B_data_out_reg = DFFE(P3_q_b[3]_PORT_B_data_out, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[0] = P3_q_b[3]_PORT_B_data_out_reg[4];

--P3_q_b[1] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[1] at M4K_X17_Y14
P3_q_b[3]_PORT_A_data_in = BUS(G2_out[3], G2_out[4], G2_out[2], G2_out[1], G2_out[0]);
P3_q_b[3]_PORT_A_data_in_reg = DFFE(P3_q_b[3]_PORT_A_data_in, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[3]_PORT_A_address_reg = DFFE(P3_q_b[3]_PORT_A_address, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[3]_PORT_B_address_reg = DFFE(P3_q_b[3]_PORT_B_address, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[3]_PORT_A_write_enable_reg = DFFE(P3_q_b[3]_PORT_A_write_enable, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_read_enable = VCC;
P3_q_b[3]_PORT_B_read_enable_reg = DFFE(P3_q_b[3]_PORT_B_read_enable, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_clock_0 = GLOBAL(M1_clk_out);
P3_q_b[3]_clock_1 = GLOBAL(M5_clk_out);
P3_q_b[3]_clock_enable_0 = H1_wrclocken;
P3_q_b[3]_clock_enable_1 = H1_rdclocken;
P3_q_b[3]_PORT_B_data_out = MEMORY(P3_q_b[3]_PORT_A_data_in_reg, , P3_q_b[3]_PORT_A_address_reg, P3_q_b[3]_PORT_B_address_reg, P3_q_b[3]_PORT_A_write_enable_reg, P3_q_b[3]_PORT_B_read_enable_reg, , , P3_q_b[3]_clock_0, P3_q_b[3]_clock_1, P3_q_b[3]_clock_enable_0, P3_q_b[3]_clock_enable_1, , );
P3_q_b[3]_PORT_B_data_out_reg = DFFE(P3_q_b[3]_PORT_B_data_out, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[1] = P3_q_b[3]_PORT_B_data_out_reg[3];

--P3_q_b[2] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[2] at M4K_X17_Y14
P3_q_b[3]_PORT_A_data_in = BUS(G2_out[3], G2_out[4], G2_out[2], G2_out[1], G2_out[0]);
P3_q_b[3]_PORT_A_data_in_reg = DFFE(P3_q_b[3]_PORT_A_data_in, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[3]_PORT_A_address_reg = DFFE(P3_q_b[3]_PORT_A_address, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[3]_PORT_B_address_reg = DFFE(P3_q_b[3]_PORT_B_address, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[3]_PORT_A_write_enable_reg = DFFE(P3_q_b[3]_PORT_A_write_enable, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_read_enable = VCC;
P3_q_b[3]_PORT_B_read_enable_reg = DFFE(P3_q_b[3]_PORT_B_read_enable, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_clock_0 = GLOBAL(M1_clk_out);
P3_q_b[3]_clock_1 = GLOBAL(M5_clk_out);
P3_q_b[3]_clock_enable_0 = H1_wrclocken;
P3_q_b[3]_clock_enable_1 = H1_rdclocken;
P3_q_b[3]_PORT_B_data_out = MEMORY(P3_q_b[3]_PORT_A_data_in_reg, , P3_q_b[3]_PORT_A_address_reg, P3_q_b[3]_PORT_B_address_reg, P3_q_b[3]_PORT_A_write_enable_reg, P3_q_b[3]_PORT_B_read_enable_reg, , , P3_q_b[3]_clock_0, P3_q_b[3]_clock_1, P3_q_b[3]_clock_enable_0, P3_q_b[3]_clock_enable_1, , );
P3_q_b[3]_PORT_B_data_out_reg = DFFE(P3_q_b[3]_PORT_B_data_out, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[2] = P3_q_b[3]_PORT_B_data_out_reg[2];

--P3_q_b[4] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[4] at M4K_X17_Y14
P3_q_b[3]_PORT_A_data_in = BUS(G2_out[3], G2_out[4], G2_out[2], G2_out[1], G2_out[0]);
P3_q_b[3]_PORT_A_data_in_reg = DFFE(P3_q_b[3]_PORT_A_data_in, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[3]_PORT_A_address_reg = DFFE(P3_q_b[3]_PORT_A_address, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[3]_PORT_B_address_reg = DFFE(P3_q_b[3]_PORT_B_address, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[3]_PORT_A_write_enable_reg = DFFE(P3_q_b[3]_PORT_A_write_enable, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_read_enable = VCC;
P3_q_b[3]_PORT_B_read_enable_reg = DFFE(P3_q_b[3]_PORT_B_read_enable, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_clock_0 = GLOBAL(M1_clk_out);
P3_q_b[3]_clock_1 = GLOBAL(M5_clk_out);
P3_q_b[3]_clock_enable_0 = H1_wrclocken;
P3_q_b[3]_clock_enable_1 = H1_rdclocken;
P3_q_b[3]_PORT_B_data_out = MEMORY(P3_q_b[3]_PORT_A_data_in_reg, , P3_q_b[3]_PORT_A_address_reg, P3_q_b[3]_PORT_B_address_reg, P3_q_b[3]_PORT_A_write_enable_reg, P3_q_b[3]_PORT_B_read_enable_reg, , , P3_q_b[3]_clock_0, P3_q_b[3]_clock_1, P3_q_b[3]_clock_enable_0, P3_q_b[3]_clock_enable_1, , );
P3_q_b[3]_PORT_B_data_out_reg = DFFE(P3_q_b[3]_PORT_B_data_out, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[4] = P3_q_b[3]_PORT_B_data_out_reg[1];


--K1_mem11[1] is RSEncoder:inst|rsenc:D|mem11[1] at LC_X13_Y15_N5
--operation mode is normal

K1_mem11[1]_lut_out = K1L48 $ K1L4 $ K1L3 $ K1_mem10[1];
K1_mem11[1] = DFFEAS(K1_mem11[1]_lut_out, GLOBAL(M5_clk_out), GLOBAL(reset), , , , , , );


--H1_data19 is RSEncoder:inst|fifo_encode:B|data19 at LC_X12_Y14_N4
--operation mode is normal

H1_data19_lut_out = H1L17 & !H1L19 & (!H1L18 # !H1L7) # !H1L17 & (H1L19 # H1L7 # H1L18);
H1_data19 = DFFEAS(H1_data19_lut_out, GLOBAL(M5_clk_out), GLOBAL(reset), , H1L6, , , , );


--L2L13 is RSEncoder:inst|Dec2Bit:E|buff~1792 at LC_X13_Y15_N0
--operation mode is normal

L2L13 = H1_data19 & (P3_q_b[3]) # !H1_data19 & (K1_mem11[1]);


--L2_cnt[0] is RSEncoder:inst|Dec2Bit:E|cnt[0] at LC_X12_Y13_N7
--operation mode is normal

L2_cnt[0]_lut_out = L2_cnt[2] # !L2_cnt[0];
L2_cnt[0] = DFFEAS(L2_cnt[0]_lut_out, GLOBAL(MC1__clk0), GLOBAL(reset), , L2_enable, , , , );


--L2_cnt[2] is RSEncoder:inst|Dec2Bit:E|cnt[2] at LC_X12_Y13_N0
--operation mode is normal

L2_cnt[2]_lut_out = L2_cnt[0] & !L2_cnt[2] & L2_cnt[1] # !L2_cnt[0] & L2_cnt[2] & !L2_cnt[1];
L2_cnt[2] = DFFEAS(L2_cnt[2]_lut_out, GLOBAL(MC1__clk0), GLOBAL(reset), , L2_enable, , , , );


--L2_cnt[1] is RSEncoder:inst|Dec2Bit:E|cnt[1] at LC_X12_Y13_N9
--operation mode is normal

L2_cnt[1]_lut_out = !L2_cnt[2] & (L2_cnt[0] $ L2_cnt[1]);
L2_cnt[1] = DFFEAS(L2_cnt[1]_lut_out, GLOBAL(MC1__clk0), GLOBAL(reset), , L2_enable, , , , );


--L2L1 is RSEncoder:inst|Dec2Bit:E|Equal~149 at LC_X12_Y13_N8
--operation mode is normal

L2L1 = !L2_cnt[1] & !L2_cnt[2];


--L2L14 is RSEncoder:inst|Dec2Bit:E|buff~1793 at LC_X13_Y13_N2
--operation mode is normal

L2_buff[3]_qfbk = L2_buff[3];
L2L14 = L2L1 & (L2_cnt[0] & L2L13 # !L2_cnt[0] & (L2_buff[3]_qfbk)) # !L2L1 & (L2_buff[3]_qfbk);

--L2_buff[3] is RSEncoder:inst|Dec2Bit:E|buff[3] at LC_X13_Y13_N2
--operation mode is normal

L2_buff[3] = DFFEAS(L2L14, GLOBAL(MC1__clk0), VCC, , L2L12, , , , );


--K1_mem11[0] is RSEncoder:inst|rsenc:D|mem11[0] at LC_X12_Y15_N0
--operation mode is normal

K1_mem11[0]_lut_out = K1L3 $ K1_mem10[0] $ K1L2 $ K1L4;
K1_mem11[0] = DFFEAS(K1_mem11[0]_lut_out, GLOBAL(M5_clk_out), GLOBAL(reset), , , , , , );


--L2L15 is RSEncoder:inst|Dec2Bit:E|buff~1794 at LC_X13_Y13_N8
--operation mode is normal

L2L15 = H1_data19 & (P3_q_b[4]) # !H1_data19 & K1_mem11[0];


--L2L16 is RSEncoder:inst|Dec2Bit:E|buff~1795 at LC_X13_Y13_N4
--operation mode is normal

L2_buff[4]_qfbk = L2_buff[4];
L2L16 = L2L1 & (L2_cnt[0] & L2L15 # !L2_cnt[0] & (L2_buff[4]_qfbk)) # !L2L1 & (L2_buff[4]_qfbk);

--L2_buff[4] is RSEncoder:inst|Dec2Bit:E|buff[4] at LC_X13_Y13_N4
--operation mode is normal

L2_buff[4] = DFFEAS(L2L16, GLOBAL(MC1__clk0), VCC, , L2L12, , , , );


--L2L2 is RSEncoder:inst|Dec2Bit:E|Select~343 at LC_X12_Y13_N5
--operation mode is normal

L2L2 = L2_cnt[1] & (L2_cnt[0]) # !L2_cnt[1] & (L2_cnt[0] & (L2L16) # !L2_cnt[0] & L2_out);


--K1_mem11[2] is RSEncoder:inst|rsenc:D|mem11[2] at LC_X12_Y15_N4
--operation mode is normal

K1_mem11[2]_lut_out = K1L1 $ K1L5 $ K1L3 $ K1_mem10[2];
K1_mem11[2] = DFFEAS(K1_mem11[2]_lut_out, GLOBAL(M5_clk_out), GLOBAL(reset), , , , , , );


--L2L17 is RSEncoder:inst|Dec2Bit:E|buff~1796 at LC_X13_Y13_N5
--operation mode is normal

L2L17 = H1_data19 & (P3_q_b[2]) # !H1_data19 & (K1_mem11[2]);


--L2L18 is RSEncoder:inst|Dec2Bit:E|buff~1797 at LC_X13_Y13_N6
--operation mode is normal

L2_buff[2]_qfbk = L2_buff[2];
L2L18 = L2L1 & (L2_cnt[0] & (L2L17) # !L2_cnt[0] & L2_buff[2]_qfbk) # !L2L1 & (L2_buff[2]_qfbk);

--L2_buff[2] is RSEncoder:inst|Dec2Bit:E|buff[2] at LC_X13_Y13_N6
--operation mode is normal

L2_buff[2] = DFFEAS(L2L18, GLOBAL(MC1__clk0), VCC, , L2L12, , , , );


--L2L3 is RSEncoder:inst|Dec2Bit:E|Select~344 at LC_X12_Y13_N2
--operation mode is normal

L2L3 = L2_cnt[1] & (L2L2 & (L2L18) # !L2L2 & L2L14) # !L2_cnt[1] & L2L2;


--L2L4 is RSEncoder:inst|Dec2Bit:E|Select~345 at LC_X12_Y13_N6
--operation mode is normal

L2L4 = L2_cnt[1] & L2_out;


--L2_buff[0] is RSEncoder:inst|Dec2Bit:E|buff[0] at LC_X13_Y13_N1
--operation mode is normal

L2_buff[0]_lut_out = L2L1 & (L2_cnt[0] & L2L19 # !L2_cnt[0] & (L2_buff[0])) # !L2L1 & (L2_buff[0]);
L2_buff[0] = DFFEAS(L2_buff[0]_lut_out, GLOBAL(MC1__clk0), VCC, , L2L12, , , , );


--L2_buff[1] is RSEncoder:inst|Dec2Bit:E|buff[1] at LC_X13_Y13_N3
--operation mode is normal

L2_buff[1]_lut_out = L2L1 & (L2_cnt[0] & L2L20 # !L2_cnt[0] & (L2_buff[1])) # !L2L1 & (L2_buff[1]);
L2_buff[1] =