top.fit.eqn

RS编码的verilog源代码

--JC9_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[2] at LC_X19_Y6_N6
--operation mode is normal

JC9_out[2]_lut_out = JC9_out[3] $ (P1_q_b[2]);
JC9_out[2] = DFFEAS(JC9_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC9_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[1] at LC_X19_Y6_N7
--operation mode is normal

JC9_out[1]_lut_out = JC9_out[4] $ JC9_out[2] $ P1_q_b[1];
JC9_out[1] = DFFEAS(JC9_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC9_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[0] at LC_X20_Y7_N8
--operation mode is normal

JC9_out[0]_lut_out = JC9_out[1] $ JC9_out[3] $ P1_q_b[0];
JC9_out[0] = DFFEAS(JC9_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L13 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~785 at LC_X22_Y6_N5
--operation mode is normal

W1L13 = JC9_out[0] # JC9_out[3] # JC9_out[2] # JC9_out[1];


--JC9_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[4] at LC_X19_Y6_N0
--operation mode is normal

JC9_out[4]_lut_out = JC9_out[0] $ JC9_out[4] $ JC9_out[2] $ P1_q_b[4];
JC9_out[4] = DFFEAS(JC9_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC10_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[3] at LC_X23_Y12_N2
--operation mode is normal

JC10_out[3]_lut_out = JC10_out[4] $ JC10_out[0] $ JC10_out[2] $ P1_q_b[3];
JC10_out[3] = DFFEAS(JC10_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC10_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[2] at LC_X23_Y12_N8
--operation mode is normal

JC10_out[2]_lut_out = JC10_out[4] $ P1_q_b[2];
JC10_out[2] = DFFEAS(JC10_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC10_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[1] at LC_X23_Y13_N6
--operation mode is normal

JC10_out[1]_lut_out = JC10_out[3] $ (P1_q_b[1]);
JC10_out[1] = DFFEAS(JC10_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L14 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~786 at LC_X23_Y6_N4
--operation mode is normal

W1L14 = JC9_out[4] # JC10_out[3] # JC10_out[1] # JC10_out[2];


--W1L15 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~787 at LC_X24_Y6_N1
--operation mode is normal

W1L15 = W1L12 # W1L14 # W1L13 # W1L11;


--JC10_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[0] at LC_X23_Y12_N3
--operation mode is normal

JC10_out[0]_lut_out = JC10_out[4] $ (JC10_out[2] $ P1_q_b[0]);
JC10_out[0] = DFFEAS(JC10_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC10_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[4] at LC_X23_Y13_N7
--operation mode is normal

JC10_out[4]_lut_out = JC10_out[1] $ P1_q_b[4] $ (JC10_out[3]);
JC10_out[4] = DFFEAS(JC10_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC11_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[3] at LC_X23_Y12_N6
--operation mode is normal

JC11_out[3]_lut_out = JC11_out[3] $ (JC11_out[1] $ P1_q_b[3]);
JC11_out[3] = DFFEAS(JC11_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC11_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[2] at LC_X23_Y12_N9
--operation mode is normal

JC11_out[2]_lut_out = JC11_out[0] $ (P1_q_b[2]);
JC11_out[2] = DFFEAS(JC11_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L16 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~788 at LC_X23_Y12_N5
--operation mode is normal

W1L16 = JC11_out[2] # JC10_out[0] # JC10_out[4] # JC11_out[3];


--JC11_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[1] at LC_X22_Y13_N7
--operation mode is normal

JC11_out[1]_lut_out = P1_q_b[1] $ (JC11_out[4]);
JC11_out[1] = DFFEAS(JC11_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC11_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[0] at LC_X23_Y12_N1
--operation mode is normal

JC11_out[0]_lut_out = JC11_out[3] $ (P1_q_b[0]);
JC11_out[0] = DFFEAS(JC11_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC11_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[4] at LC_X23_Y12_N7
--operation mode is normal

JC11_out[4]_lut_out = JC11_out[2] $ (JC11_out[4] $ P1_q_b[4]);
JC11_out[4] = DFFEAS(JC11_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC12_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[3] at LC_X23_Y12_N4
--operation mode is normal

JC12_out[3]_lut_out = JC12_out[2] $ (JC12_out[4] $ P1_q_b[3]);
JC12_out[3] = DFFEAS(JC12_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L17 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~789 at LC_X23_Y12_N0
--operation mode is normal

W1L17 = JC11_out[4] # JC12_out[3] # JC11_out[1] # JC11_out[0];


--JC12_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[2] at LC_X24_Y13_N1
--operation mode is normal

JC12_out[2]_lut_out = JC12_out[1] $ P1_q_b[2];
JC12_out[2] = DFFEAS(JC12_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC12_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[1] at LC_X24_Y13_N9
--operation mode is normal

JC12_out[1]_lut_out = JC12_out[0] $ P1_q_b[1];
JC12_out[1] = DFFEAS(JC12_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC12_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[0] at LC_X24_Y13_N8
--operation mode is normal

JC12_out[0]_lut_out = JC12_out[4] $ P1_q_b[0];
JC12_out[0] = DFFEAS(JC12_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC12_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[4] at LC_X24_Y13_N3
--operation mode is normal

JC12_out[4]_lut_out = JC12_out[3] $ (P1_q_b[4]);
JC12_out[4] = DFFEAS(JC12_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L18 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~790 at LC_X24_Y11_N9
--operation mode is normal

W1L18 = JC12_out[4] # JC12_out[0] # JC12_out[1] # JC12_out[2];


--W1L19 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~791 at LC_X24_Y6_N2
--operation mode is normal

W1L19 = W1L17 # W1L18 # W1L16 # W1L15;


--Y1L47 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|nxt_state1.st1_4~10 at LC_X24_Y6_N8
--operation mode is normal

Y1L47 = W1_state.st2 & (W1L19 # W1L10 # W1L5);


--M3_clk_temp1 is RSDecoder:inst1|divide5:dividec|clk_temp1 at LC_X8_Y10_N5
--operation mode is normal

M3_clk_temp1_lut_out = M3_clk_temp1 $ (!M3_counter[0] & (M3_counter[1] $ M3_counter[2]));
M3_clk_temp1 = DFFEAS(M3_clk_temp1_lut_out, GLOBAL(clk), VCC, , , , , , );


--M3_clk_out is RSDecoder:inst1|divide5:dividec|clk_out at LC_X8_Y10_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M3_clk_temp2_qfbk = M3_clk_temp2;
M3_clk_out = M3_clk_temp2_qfbk # M3_clk_temp1;

--M3_clk_temp2 is RSDecoder:inst1|divide5:dividec|clk_temp2 at LC_X8_Y10_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M3_clk_temp2 = DFFEAS(M3_clk_out, !GLOBAL(clk), VCC, , , M3_clk_temp1, , , VCC);


--Y1_state2.st2_10 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_10 at LC_X25_Y4_N2
--operation mode is normal

Y1_state2.st2_10_lut_out = Y1_state2.st2_9 & !Y1_lastdataout & (Y1L5);
Y1_state2.st2_10 = DFFEAS(Y1_state2.st2_10_lut_out, !GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1_state2.st2_7 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_7 at LC_X25_Y4_N7
--operation mode is normal

Y1_state2.st2_7_lut_out = Y1_state2.st2_6 & (Y1L8 & !Y1_lastdataout);
Y1_state2.st2_7 = DFFEAS(Y1_state2.st2_7_lut_out, !GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1_state2.st2_11 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_11 at LC_X25_Y4_N6
--operation mode is normal

Y1_state2.st2_11_lut_out = Y1_state2.st2_9 & !Y1_lastdataout & (!Y1L5);
Y1_state2.st2_11 = DFFEAS(Y1_state2.st2_11_lut_out, !GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1L52 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|reduce_or~82 at LC_X24_Y6_N9
--operation mode is normal

Y1L52 = Y1_state2.st2_7 # Y1_state2.st2_11 # Y1_state2.st2_10;


--Y1_state1.st1_9 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_9 at LC_X24_Y5_N6
--operation mode is normal

Y1_state1.st1_9_lut_out = !Y1L52 & (Y1_state1.st1_9 # Y1_state1.st1_8);
Y1_state1.st1_9 = DFFEAS(Y1_state1.st1_9_lut_out, GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1_state1.st1_8 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_8 at LC_X24_Y5_N5
--operation mode is normal

Y1_state1.st1_8_lut_out = Y1_state1.st1_7 & R1_wordstart & !Y1L52;
Y1_state1.st1_8 = DFFEAS(Y1_state1.st1_8_lut_out, GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--U1_rootcntr[1] is RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|rootcntr[1] at LC_X22_Y5_N1
--operation mode is normal

U1_rootcntr[1]_lut_out = U1_rootcntr[1] $ (U1_rootcntr[0] & !U1L32);
U1_rootcntr[1] = DFFEAS(U1_rootcntr[1]_lut_out, !GLOBAL(M3_clk_out), VCC, , , , , !U1_state, );


--SB25_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12|register_pe:reg1|out[4] at LC_X19_Y9_N6
--operation mode is normal

SB25_out[4]_lut_out = KB26L5 $ KB25_intvald[0] $ KB25L5 $ KB26_intvald[0];
SB25_out[4] = DFFEAS(SB25_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , QB1_hold, , , !QB1_state.st2, );


--V1L7 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp6~41 at LC_X19_Y9_N0
--operation mode is normal

V1L7 = SB25_out[1] # SB25_out[4];


--V1_koefcomp6 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp6 at LC_X19_Y9_N7
--operation mode is normal

V1_koefcomp6 = SB25_out[3] # V1L7 # SB25_out[2] # SB25_out[0];


--RB1L1 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out[0]~421 at LC_X23_Y4_N0
--operation mode is normal

RB1L1 = !SB17_out[1] & (!SB17_out[4]);


--SB17_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[2] at LC_X22_Y6_N4
--operation mode is normal

SB17_out[2]_lut_out = MB9L27;
SB17_out[2] = DFFEAS(SB17_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , QB1_hold, JC9_out[2], , SB9L7, QB1_state.st1);


--SB17_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[0] at LC_X22_Y6_N2
--operation mode is normal

SB17_out[0]_lut_out = MB9_outadder[0];
SB17_out[0] = DFFEAS(SB17_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , QB1_hold, JC9_out[0], , SB9L7, QB1_state.st1);


--RB1L2 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out[0]~422 at LC_X23_Y4_N5