top.fit.eqn

RS编码的verilog源代码

KC1_clk_temp1_lut_out = KC1_clk_temp1 $ (!KC1_counter[2] & (KC1_counter[1] $ KC1_counter[0]));
KC1_clk_temp1 = DFFEAS(KC1_clk_temp1_lut_out, GLOBAL(clk), VCC, , , , , , );


--KC1_clk_out is Clock:inst3|divide3:divideb|clk_out at LC_X8_Y10_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

KC1_clk_temp2_qfbk = KC1_clk_temp2;
KC1_clk_out = KC1_clk_temp2_qfbk # KC1_clk_temp1;

--KC1_clk_temp2 is Clock:inst3|divide3:divideb|clk_temp2 at LC_X8_Y10_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

KC1_clk_temp2 = DFFEAS(KC1_clk_out, !GLOBAL(clk), VCC, , , KC1_clk_temp1, , , VCC);


--L1_enable is RSDecoder:inst1|Dec2Bit:Dec2Bit|enable at LC_X19_Y11_N5
--operation mode is normal

L1_enable_lut_out = VCC;
L1_enable = DFFEAS(L1_enable_lut_out, !S1_wordstart, GLOBAL(reset), , , , , , );


--Y1_state1.st1_3 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_3 at LC_X24_Y5_N7
--operation mode is normal

Y1_state1.st1_3_lut_out = Y1_state2.st2_10 & (Y1_state1.st1_11 # Y1_state1.st1_2) # !Y1_state2.st2_10 & Y1_state2.st2_2 & (Y1_state1.st1_11 # Y1_state1.st1_2);
Y1_state1.st1_3 = DFFEAS(Y1_state1.st1_3_lut_out, GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--W1_state.st2 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state.st2 at LC_X25_Y5_N5
--operation mode is normal

W1_state.st2_lut_out = Y1_state1.st1_3 & W1_state.st1;
W1_state.st2 = DFFEAS(W1_state.st2_lut_out, !GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--JC1_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[3] at LC_X22_Y13_N2
--operation mode is normal

JC1_out[3]_lut_out = JC1_out[4] $ JC1_out[0] $ P1_q_b[3];
JC1_out[3] = DFFEAS(JC1_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC1_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[1] at LC_X22_Y13_N0
--operation mode is normal

JC1_out[1]_lut_out = P1_q_b[1] $ JC1_out[2] $ JC1_out[3] $ JC1_out[0];
JC1_out[1] = DFFEAS(JC1_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC1_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[0] at LC_X22_Y13_N5
--operation mode is normal

JC1_out[0]_lut_out = JC1_out[1] $ JC1_out[2] $ P1_q_b[0];
JC1_out[0] = DFFEAS(JC1_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L1 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~773 at LC_X22_Y13_N8
--operation mode is normal

W1L1 = JC1_out[3] # JC1_out[1] # JC1_out[2] # JC1_out[0];


--JC1_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[4] at LC_X22_Y13_N1
--operation mode is normal

JC1_out[4]_lut_out = JC1_out[1] $ JC1_out[0] $ P1_q_b[4];
JC1_out[4] = DFFEAS(JC1_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC2_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[3] at LC_X22_Y13_N9
--operation mode is normal

JC2_out[3]_lut_out = JC2_out[1] $ (P1_q_b[3] $ JC2_out[0]);
JC2_out[3] = DFFEAS(JC2_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L2 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~774 at LC_X22_Y13_N6
--operation mode is normal

W1L2 = JC2_out[1] # JC2_out[2] # JC2_out[3] # JC1_out[4];


--JC2_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[0] at LC_X23_Y13_N9
--operation mode is normal

JC2_out[0]_lut_out = JC2_out[0] $ JC2_out[3] $ JC2_out[2] $ P1_q_b[0];
JC2_out[0] = DFFEAS(JC2_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC2_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[4] at LC_X23_Y13_N3
--operation mode is normal

JC2_out[4]_lut_out = JC2_out[2] $ JC2_out[1] $ P1_q_b[4];
JC2_out[4] = DFFEAS(JC2_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC3_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[3] at LC_X25_Y13_N6
--operation mode is normal

JC3_out[3]_lut_out = JC3_out[1] $ P1_q_b[3] $ JC3_out[2];
JC3_out[3] = DFFEAS(JC3_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC3_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[2] at LC_X25_Y13_N3
--operation mode is normal

JC3_out[2]_lut_out = JC3_out[3] $ JC3_out[1] $ P1_q_b[2] $ JC3_out[2];
JC3_out[2] = DFFEAS(JC3_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L3 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~775 at LC_X23_Y13_N5
--operation mode is normal

W1L3 = JC2_out[0] # JC3_out[2] # JC3_out[3] # JC2_out[4];


--JC3_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[4] at LC_X25_Y13_N7
--operation mode is normal

JC3_out[4]_lut_out = JC3_out[3] $ P1_q_b[4] $ JC3_out[0] $ JC3_out[2];
JC3_out[4] = DFFEAS(JC3_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC4_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[3] at LC_X25_Y13_N0
--operation mode is normal

JC4_out[3]_lut_out = JC4_out[0] $ JC4_out[3] $ P1_q_b[3] $ JC4_out[2];
JC4_out[3] = DFFEAS(JC4_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L4 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~776 at LC_X25_Y13_N4
--operation mode is normal

W1L4 = JC3_out[4] # JC3_out[1] # JC3_out[0] # JC4_out[3];


--W1L5 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~777 at LC_X23_Y13_N2
--operation mode is normal

W1L5 = W1L1 # W1L3 # W1L4 # W1L2;


--JC4_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[1] at LC_X24_Y13_N7
--operation mode is normal

JC4_out[1]_lut_out = JC4_out[1] $ JC4_out[2] $ JC4_out[3] $ P1_q_b[1];
JC4_out[1] = DFFEAS(JC4_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L6 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~778 at LC_X24_Y13_N4
--operation mode is normal

W1L6 = JC4_out[0] # JC4_out[2] # JC4_out[1] # JC4_out[4];


--JC5_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[2] at LC_X19_Y6_N9
--operation mode is normal

JC5_out[2]_lut_out = P1_q_b[2] $ JC5_out[1] $ JC5_out[4] $ JC5_out[3];
JC5_out[2] = DFFEAS(JC5_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC5_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[0] at LC_X19_Y6_N4
--operation mode is normal

JC5_out[0]_lut_out = P1_q_b[0] $ JC5_out[3] $ JC5_out[2] $ JC5_out[1];
JC5_out[0] = DFFEAS(JC5_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L7 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~779 at LC_X19_Y7_N6
--operation mode is normal

W1L7 = JC5_out[3] # JC5_out[2] # JC5_out[0] # JC5_out[1];


--JC6_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[2] at LC_X19_Y5_N5
--operation mode is normal

JC6_out[2]_lut_out = JC6_out[4] $ JC6_out[2] $ JC6_out[0] $ P1_q_b[2];
JC6_out[2] = DFFEAS(JC6_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC6_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[1] at LC_X19_Y5_N9
--operation mode is normal

JC6_out[1]_lut_out = JC6_out[4] $ JC6_out[3] $ JC6_out[1] $ P1_q_b[1];
JC6_out[1] = DFFEAS(JC6_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L8 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~780 at LC_X19_Y5_N4
--operation mode is normal

W1L8 = JC6_out[1] # JC6_out[3] # JC5_out[4] # JC6_out[2];


--JC6_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[4] at LC_X19_Y5_N6
--operation mode is normal

JC6_out[4]_lut_out = P1_q_b[4] $ JC6_out[2] $ JC6_out[1] $ JC6_out[3];
JC6_out[4] = DFFEAS(JC6_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC7_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[3] at LC_X19_Y5_N8
--operation mode is normal

JC7_out[3]_lut_out = JC7_out[1] $ JC7_out[3] $ P1_q_b[3] $ JC7_out[2];
JC7_out[3] = DFFEAS(JC7_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC7_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[2] at LC_X19_Y5_N3
--operation mode is normal

JC7_out[2]_lut_out = JC7_out[1] $ (JC7_out[3] $ P1_q_b[2]);
JC7_out[2] = DFFEAS(JC7_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L9 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~781 at LC_X19_Y5_N1
--operation mode is normal

W1L9 = JC6_out[4] # JC7_out[3] # JC6_out[0] # JC7_out[2];


--W1L10 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~782 at LC_X19_Y7_N2
--operation mode is normal

W1L10 = W1L8 # W1L9 # W1L6 # W1L7;


--JC7_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[1] at LC_X21_Y4_N3
--operation mode is normal

JC7_out[1]_lut_out = JC7_out[2] $ JC7_out[4] $ JC7_out[0] $ P1_q_b[1];
JC7_out[1] = DFFEAS(JC7_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC7_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[0] at LC_X21_Y4_N8
--operation mode is normal

JC7_out[0]_lut_out = JC7_out[4] $ JC7_out[1] $ JC7_out[3] $ P1_q_b[0];
JC7_out[0] = DFFEAS(JC7_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L11 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~783 at LC_X21_Y4_N6
--operation mode is normal

W1L11 = JC8_out[3] # JC7_out[4] # JC7_out[0] # JC7_out[1];


--JC8_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[2] at LC_X21_Y4_N1
--operation mode is normal

JC8_out[2]_lut_out = JC8_out[2] $ P1_q_b[2] $ JC8_out[4];
JC8_out[2] = DFFEAS(JC8_out[2]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC8_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[1] at LC_X21_Y4_N2
--operation mode is normal

JC8_out[1]_lut_out = JC8_out[1] $ (JC8_out[3] $ P1_q_b[1]);
JC8_out[1] = DFFEAS(JC8_out[1]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC8_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[0] at LC_X21_Y4_N5
--operation mode is normal

JC8_out[0]_lut_out = JC8_out[2] $ JC8_out[0] $ JC8_out[4] $ P1_q_b[0];
JC8_out[0] = DFFEAS(JC8_out[0]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--JC8_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[4] at LC_X21_Y4_N9
--operation mode is normal

JC8_out[4]_lut_out = JC8_out[4] $ JC8_out[3] $ JC8_out[1] $ P1_q_b[4];
JC8_out[4] = DFFEAS(JC8_out[4]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );


--W1L12 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~784 at LC_X21_Y4_N4
--operation mode is normal

W1L12 = JC8_out[1] # JC8_out[0] # JC8_out[4] # JC8_out[2];


--JC9_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[3] at LC_X19_Y6_N1
--operation mode is normal

JC9_out[3]_lut_out = JC9_out[1] $ JC9_out[4] $ P1_q_b[3] $ JC9_out[3];
JC9_out[3] = DFFEAS(JC9_out[3]_lut_out, GLOBAL(M3_clk_out), VCC, , !Y1_state2.st2_3, , , Y1L50, );