top.fit.eqn

RS编码的verilog源代码

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--L1_out is RSDecoder:inst1|Dec2Bit:Dec2Bit|out at LC_X20_Y11_N3
--operation mode is normal

L1_out_lut_out = L1_cnt[2] & (L1L3) # !L1_cnt[2] & L1L5;
L1_out = DFFEAS(L1_out_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , L1_enable, , , , );


--L1_outstart is RSDecoder:inst1|Dec2Bit:Dec2Bit|outstart at LC_X20_Y11_N9
--operation mode is normal

L1_outstart_lut_out = !L1_cnt[1] & !L1_cnt[2] & !L1_cnt[0];
L1_outstart = DFFEAS(L1_outstart_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , L1_enable, , , , );


--Y1_state1.st1_4 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_4 at LC_X24_Y6_N5
--operation mode is normal

Y1_state1.st1_4_lut_out = Y1L47 & Y1_state1.st1_3;
Y1_state1.st1_4 = DFFEAS(Y1_state1.st1_4_lut_out, GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1_state1.st1_11 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_11 at LC_X24_Y5_N3
--operation mode is normal

Y1_state1.st1_11_lut_out = !Y1L3 & Y1L52 & (Y1_state1.st1_9 # Y1_state1.st1_8);
Y1_state1.st1_11 = DFFEAS(Y1_state1.st1_11_lut_out, GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1_state1.st1_10 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_10 at LC_X23_Y5_N7
--operation mode is normal

Y1_state1.st1_10_lut_out = Y1_state1.st1_7 & Y1L52 & !Y1L3;
Y1_state1.st1_10 = DFFEAS(Y1_state1.st1_10_lut_out, GLOBAL(M3_clk_out), GLOBAL(reset), , , , , , );


--Y1_decode_fail is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|decode_fail at LC_X24_Y5_N2
--operation mode is normal

Y1_decode_fail = Y1_state1.st1_11 # Y1_state1.st1_10;


--D1_out is nrz:inst2|out at LC_X13_Y8_N9
--operation mode is normal

D1_out_lut_out = D1_c5;
D1_out = DFFEAS(D1_out_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , , , , , );


--D1_datastart is nrz:inst2|datastart at LC_X12_Y9_N5
--operation mode is normal

D1_datastart_lut_out = D1_cnt[1] & (D1_cnt[0] & !D1_cnt[2] # !D1_cnt[0] & (D1_datastart)) # !D1_cnt[1] & D1_datastart & (D1_cnt[0] # !D1_cnt[2]);
D1_datastart = DFFEAS(D1_datastart_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , , , , , );


--F1_errorout is error:inst6|errorout at LC_X10_Y13_N4
--operation mode is normal

F1_errorout_lut_out = F1L4 & (F1_cnt[1] & !F1L1 & !F1_cnt[6] # !F1_cnt[1] & (F1L1 $ F1_cnt[6]));
F1_errorout = DFFEAS(F1_errorout_lut_out, GLOBAL(MC1__clk0), VCC, , , , , , );


--inst17 is inst17 at LC_X12_Y13_N4
--operation mode is normal

inst17_lut_out = L2_out $ (F1_errorout);
inst17 = DFFEAS(inst17_lut_out, GLOBAL(MC1__clk0), VCC, , , , , , );


--L2_out is RSEncoder:inst|Dec2Bit:E|out at LC_X12_Y13_N3
--operation mode is normal

L2_out_lut_out = L2_cnt[2] & (L2L4 # L2L5) # !L2_cnt[2] & (L2L3);
L2_out = DFFEAS(L2_out_lut_out, GLOBAL(MC1__clk0), GLOBAL(reset), , L2_enable, , , , );


--L1_buff[0] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] at LC_X19_Y11_N3
--operation mode is normal

L1_buff[0]_lut_out = L1L1 & (L1_cnt[0] & (P2_q_b[0]) # !L1_cnt[0] & L1_buff[0]) # !L1L1 & L1_buff[0];
L1_buff[0] = DFFEAS(L1_buff[0]_lut_out, GLOBAL(KC1_clk_out), VCC, , L1L12, , , , );


--L1_buff[1] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[1] at LC_X19_Y11_N2
--operation mode is normal

L1_buff[1]_lut_out = L1L1 & (L1_cnt[0] & P2_q_b[1] # !L1_cnt[0] & (L1_buff[1])) # !L1L1 & (L1_buff[1]);
L1_buff[1] = DFFEAS(L1_buff[1]_lut_out, GLOBAL(KC1_clk_out), VCC, , L1L12, , , , );


--L1_cnt[0] is RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[0] at LC_X20_Y11_N1
--operation mode is normal

L1_cnt[0]_lut_out = L1_cnt[2] # !L1_cnt[0];
L1_cnt[0] = DFFEAS(L1_cnt[0]_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , L1_enable, , , , );


--L1L2 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~317 at LC_X19_Y11_N0
--operation mode is normal

L1L2 = L1_cnt[0] & (L1_buff[0]) # !L1_cnt[0] & (L1_buff[1]);


--L1_cnt[1] is RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[1] at LC_X20_Y11_N5
--operation mode is normal

L1_cnt[1]_lut_out = !L1_cnt[2] & (L1_cnt[1] $ L1_cnt[0]);
L1_cnt[1] = DFFEAS(L1_cnt[1]_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , L1_enable, , , , );


--L1L3 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~318 at LC_X20_Y11_N0
--operation mode is normal

L1L3 = L1_cnt[1] & (L1_out) # !L1_cnt[1] & L1L2;


--P2_q_b[3] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3] at M4K_X17_Y11
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 5, Port B Depth: 32, Port B Width: 5
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P2_q_b[3]_PORT_A_data_in = BUS(X13_out[1], X13_out[0], X13_out[2], X13_out[4], X13_out[3]);
P2_q_b[3]_PORT_A_data_in_reg = DFFE(P2_q_b[3]_PORT_A_data_in, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[3]_PORT_A_address_reg = DFFE(P2_q_b[3]_PORT_A_address, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[3]_PORT_B_address_reg = DFFE(P2_q_b[3]_PORT_B_address, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_PORT_A_write_enable = S1_wren;
P2_q_b[3]_PORT_A_write_enable_reg = DFFE(P2_q_b[3]_PORT_A_write_enable, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_read_enable = VCC;
P2_q_b[3]_PORT_B_read_enable_reg = DFFE(P2_q_b[3]_PORT_B_read_enable, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_clock_0 = GLOBAL(M3_clk_out);
P2_q_b[3]_clock_1 = GLOBAL(M1_clk_out);
P2_q_b[3]_clock_enable_0 = S1_wrclocken;
P2_q_b[3]_clock_enable_1 = S1_rdclocken;
P2_q_b[3]_PORT_B_data_out = MEMORY(P2_q_b[3]_PORT_A_data_in_reg, , P2_q_b[3]_PORT_A_address_reg, P2_q_b[3]_PORT_B_address_reg, P2_q_b[3]_PORT_A_write_enable_reg, P2_q_b[3]_PORT_B_read_enable_reg, , , P2_q_b[3]_clock_0, P2_q_b[3]_clock_1, P2_q_b[3]_clock_enable_0, P2_q_b[3]_clock_enable_1, , );
P2_q_b[3]_PORT_B_data_out_reg = DFFE(P2_q_b[3]_PORT_B_data_out, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3] = P2_q_b[3]_PORT_B_data_out_reg[0];

--P2_q_b[1] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[1] at M4K_X17_Y11
P2_q_b[3]_PORT_A_data_in = BUS(X13_out[1], X13_out[0], X13_out[2], X13_out[4], X13_out[3]);
P2_q_b[3]_PORT_A_data_in_reg = DFFE(P2_q_b[3]_PORT_A_data_in, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[3]_PORT_A_address_reg = DFFE(P2_q_b[3]_PORT_A_address, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[3]_PORT_B_address_reg = DFFE(P2_q_b[3]_PORT_B_address, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_PORT_A_write_enable = S1_wren;
P2_q_b[3]_PORT_A_write_enable_reg = DFFE(P2_q_b[3]_PORT_A_write_enable, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_read_enable = VCC;
P2_q_b[3]_PORT_B_read_enable_reg = DFFE(P2_q_b[3]_PORT_B_read_enable, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_clock_0 = GLOBAL(M3_clk_out);
P2_q_b[3]_clock_1 = GLOBAL(M1_clk_out);
P2_q_b[3]_clock_enable_0 = S1_wrclocken;
P2_q_b[3]_clock_enable_1 = S1_rdclocken;
P2_q_b[3]_PORT_B_data_out = MEMORY(P2_q_b[3]_PORT_A_data_in_reg, , P2_q_b[3]_PORT_A_address_reg, P2_q_b[3]_PORT_B_address_reg, P2_q_b[3]_PORT_A_write_enable_reg, P2_q_b[3]_PORT_B_read_enable_reg, , , P2_q_b[3]_clock_0, P2_q_b[3]_clock_1, P2_q_b[3]_clock_enable_0, P2_q_b[3]_clock_enable_1, , );
P2_q_b[3]_PORT_B_data_out_reg = DFFE(P2_q_b[3]_PORT_B_data_out, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[1] = P2_q_b[3]_PORT_B_data_out_reg[4];

--P2_q_b[0] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[0] at M4K_X17_Y11
P2_q_b[3]_PORT_A_data_in = BUS(X13_out[1], X13_out[0], X13_out[2], X13_out[4], X13_out[3]);
P2_q_b[3]_PORT_A_data_in_reg = DFFE(P2_q_b[3]_PORT_A_data_in, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[3]_PORT_A_address_reg = DFFE(P2_q_b[3]_PORT_A_address, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[3]_PORT_B_address_reg = DFFE(P2_q_b[3]_PORT_B_address, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_PORT_A_write_enable = S1_wren;
P2_q_b[3]_PORT_A_write_enable_reg = DFFE(P2_q_b[3]_PORT_A_write_enable, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_read_enable = VCC;
P2_q_b[3]_PORT_B_read_enable_reg = DFFE(P2_q_b[3]_PORT_B_read_enable, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_clock_0 = GLOBAL(M3_clk_out);
P2_q_b[3]_clock_1 = GLOBAL(M1_clk_out);
P2_q_b[3]_clock_enable_0 = S1_wrclocken;
P2_q_b[3]_clock_enable_1 = S1_rdclocken;
P2_q_b[3]_PORT_B_data_out = MEMORY(P2_q_b[3]_PORT_A_data_in_reg, , P2_q_b[3]_PORT_A_address_reg, P2_q_b[3]_PORT_B_address_reg, P2_q_b[3]_PORT_A_write_enable_reg, P2_q_b[3]_PORT_B_read_enable_reg, , , P2_q_b[3]_clock_0, P2_q_b[3]_clock_1, P2_q_b[3]_clock_enable_0, P2_q_b[3]_clock_enable_1, , );
P2_q_b[3]_PORT_B_data_out_reg = DFFE(P2_q_b[3]_PORT_B_data_out, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[0] = P2_q_b[3]_PORT_B_data_out_reg[3];

--P2_q_b[2] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[2] at M4K_X17_Y11
P2_q_b[3]_PORT_A_data_in = BUS(X13_out[1], X13_out[0], X13_out[2], X13_out[4], X13_out[3]);
P2_q_b[3]_PORT_A_data_in_reg = DFFE(P2_q_b[3]_PORT_A_data_in, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[3]_PORT_A_address_reg = DFFE(P2_q_b[3]_PORT_A_address, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[3]_PORT_B_address_reg = DFFE(P2_q_b[3]_PORT_B_address, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_PORT_A_write_enable = S1_wren;
P2_q_b[3]_PORT_A_write_enable_reg = DFFE(P2_q_b[3]_PORT_A_write_enable, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_read_enable = VCC;
P2_q_b[3]_PORT_B_read_enable_reg = DFFE(P2_q_b[3]_PORT_B_read_enable, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_clock_0 = GLOBAL(M3_clk_out);
P2_q_b[3]_clock_1 = GLOBAL(M1_clk_out);
P2_q_b[3]_clock_enable_0 = S1_wrclocken;
P2_q_b[3]_clock_enable_1 = S1_rdclocken;
P2_q_b[3]_PORT_B_data_out = MEMORY(P2_q_b[3]_PORT_A_data_in_reg, , P2_q_b[3]_PORT_A_address_reg, P2_q_b[3]_PORT_B_address_reg, P2_q_b[3]_PORT_A_write_enable_reg, P2_q_b[3]_PORT_B_read_enable_reg, , , P2_q_b[3]_clock_0, P2_q_b[3]_clock_1, P2_q_b[3]_clock_enable_0, P2_q_b[3]_clock_enable_1, , );
P2_q_b[3]_PORT_B_data_out_reg = DFFE(P2_q_b[3]_PORT_B_data_out, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[2] = P2_q_b[3]_PORT_B_data_out_reg[2];

--P2_q_b[4] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[4] at M4K_X17_Y11
P2_q_b[3]_PORT_A_data_in = BUS(X13_out[1], X13_out[0], X13_out[2], X13_out[4], X13_out[3]);
P2_q_b[3]_PORT_A_data_in_reg = DFFE(P2_q_b[3]_PORT_A_data_in, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[3]_PORT_A_address_reg = DFFE(P2_q_b[3]_PORT_A_address, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[3]_PORT_B_address_reg = DFFE(P2_q_b[3]_PORT_B_address, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_PORT_A_write_enable = S1_wren;
P2_q_b[3]_PORT_A_write_enable_reg = DFFE(P2_q_b[3]_PORT_A_write_enable, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_read_enable = VCC;
P2_q_b[3]_PORT_B_read_enable_reg = DFFE(P2_q_b[3]_PORT_B_read_enable, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_clock_0 = GLOBAL(M3_clk_out);
P2_q_b[3]_clock_1 = GLOBAL(M1_clk_out);
P2_q_b[3]_clock_enable_0 = S1_wrclocken;
P2_q_b[3]_clock_enable_1 = S1_rdclocken;
P2_q_b[3]_PORT_B_data_out = MEMORY(P2_q_b[3]_PORT_A_data_in_reg, , P2_q_b[3]_PORT_A_address_reg, P2_q_b[3]_PORT_B_address_reg, P2_q_b[3]_PORT_A_write_enable_reg, P2_q_b[3]_PORT_B_read_enable_reg, , , P2_q_b[3]_clock_0, P2_q_b[3]_clock_1, P2_q_b[3]_clock_enable_0, P2_q_b[3]_clock_enable_1, , );
P2_q_b[3]_PORT_B_data_out_reg = DFFE(P2_q_b[3]_PORT_B_data_out, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[4] = P2_q_b[3]_PORT_B_data_out_reg[1];


--L1_cnt[2] is RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[2] at LC_X20_Y11_N4
--operation mode is normal

L1_cnt[2]_lut_out = L1_cnt[1] & !L1_cnt[2] & L1_cnt[0] # !L1_cnt[1] & L1_cnt[2] & !L1_cnt[0];
L1_cnt[2] = DFFEAS(L1_cnt[2]_lut_out, GLOBAL(KC1_clk_out), GLOBAL(reset), , L1_enable, , , , );


--L1L1 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Equal~149 at LC_X20_Y11_N6
--operation mode is normal

L1L1 = !L1_cnt[2] & !L1_cnt[1];


--L1L13 is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1117 at LC_X19_Y11_N6
--operation mode is normal

L1_buff[3]_qfbk = L1_buff[3];
L1L13 = L1L1 & (L1_cnt[0] & P2_q_b[3] # !L1_cnt[0] & (L1_buff[3]_qfbk)) # !L1L1 & (L1_buff[3]_qfbk);

--L1_buff[3] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[3] at LC_X19_Y11_N6
--operation mode is normal

L1_buff[3] = DFFEAS(L1L13, GLOBAL(KC1_clk_out), VCC, , L1L12, , , , );


--L1L14 is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1118 at LC_X19_Y11_N8
--operation mode is normal

L1_buff[4]_qfbk = L1_buff[4];
L1L14 = L1L1 & (L1_cnt[0] & P2_q_b[4] # !L1_cnt[0] & (L1_buff[4]_qfbk)) # !L1L1 & (L1_buff[4]_qfbk);

--L1_buff[4] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4] at LC_X19_Y11_N8
--operation mode is normal

L1_buff[4] = DFFEAS(L1L14, GLOBAL(KC1_clk_out), VCC, , L1L12, , , , );


--L1L4 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~319 at LC_X20_Y11_N2
--operation mode is normal

L1L4 = L1_cnt[0] & (L1_cnt[1] # L1L14) # !L1_cnt[0] & !L1_cnt[1] & (L1_out);


--L1L15 is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1119 at LC_X19_Y11_N4
--operation mode is normal

L1_buff[2]_qfbk = L1_buff[2];
L1L15 = L1L1 & (L1_cnt[0] & P2_q_b[2] # !L1_cnt[0] & (L1_buff[2]_qfbk)) # !L1L1 & (L1_buff[2]_qfbk);

--L1_buff[2] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[2] at LC_X19_Y11_N4
--operation mode is normal

L1_buff[2] = DFFEAS(L1L15, GLOBAL(KC1_clk_out), VCC, , L1L12, , , , );


--L1L5 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~320 at LC_X20_Y11_N7
--operation mode is normal

L1L5 = L1L4 & (L1L15 # !L1_cnt[1]) # !L1L4 & L1L13 & (L1_cnt[1]);


--KC1_clk_temp1 is Clock:inst3|divide3:divideb|clk_temp1 at LC_X8_Y10_N3
--operation mode is normal