top.map.rpt

RS编码的verilog源代码

Analysis & Synthesis report for top
Wed Jun 13 09:43:29 2007
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1
  9. State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2
 10. State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol|state
 11. State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state
 12. User-Specified and Inferred Latches
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (Restructuring Performed)
 16. Source assignments for RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
 17. Source assignments for RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
 18. Source assignments for RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
 19. Parameter Settings for User Entity Instance: RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component
 20. Parameter Settings for User Entity Instance: RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock
 21. Parameter Settings for User Entity Instance: RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|control:mcontrol
 22. Parameter Settings for User Entity Instance: RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock
 23. Parameter Settings for User Entity Instance: RSDecoder:inst1|rsdec:rsdec|MainControl:controller
 24. Parameter Settings for User Entity Instance: RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component
 25. Parameter Settings for User Entity Instance: Clock:inst3|pll:p31_57|altpll:altpll_component
 26. Parameter Settings for User Entity Instance: RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component
 27. Analysis & Synthesis Equations
 28. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jun 13 09:43:29 2007         ;
; Quartus II Version          ; 5.1 Build 216 03/06/2006 SP 2 SJ Full Version ;
; Revision Name               ; top                                           ;
; Top-level Entity Name       ; rs                                            ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 1,697                                         ;
; Total pins                  ; 11                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 480                                           ;
; Total PLLs                  ; 1                                             ;
+-----------------------------+-----------------------------------------------+