top.map.eqn

RS编码的verilog源代码

F1L11 = CARRY(F1_cnt[2] & (!F1L9));


--F1_cnt[7] is error:inst6|cnt[7]
--operation mode is normal

F1_cnt[7]_carry_eqn = F1L19;
F1_cnt[7]_lut_out = F1_cnt[7] $ (F1_cnt[7]_carry_eqn);
F1_cnt[7] = DFFEAS(F1_cnt[7]_lut_out, MC1__clk0, VCC, , , , , , );


--F1L1 is error:inst6|always0~617
--operation mode is normal

F1L1 = F1_cnt[2] # F1_cnt[7] & F1_cnt[4] # !F1_cnt[7] & (F1_cnt[5]);


--F1_cnt[1] is error:inst6|cnt[1]
--operation mode is arithmetic

F1_cnt[1]_carry_eqn = F1L7;
F1_cnt[1]_lut_out = F1_cnt[1] $ (F1_cnt[1]_carry_eqn);
F1_cnt[1] = DFFEAS(F1_cnt[1]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L9 is error:inst6|cnt[1]~77
--operation mode is arithmetic

F1L9 = CARRY(!F1L7 # !F1_cnt[1]);


--F1_cnt[0] is error:inst6|cnt[0]
--operation mode is arithmetic

F1_cnt[0]_lut_out = !F1_cnt[0];
F1_cnt[0] = DFFEAS(F1_cnt[0]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L7 is error:inst6|cnt[0]~81
--operation mode is arithmetic

F1L7 = CARRY(F1_cnt[0]);


--F1_cnt[3] is error:inst6|cnt[3]
--operation mode is arithmetic

F1_cnt[3]_carry_eqn = F1L11;
F1_cnt[3]_lut_out = F1_cnt[3] $ (F1_cnt[3]_carry_eqn);
F1_cnt[3] = DFFEAS(F1_cnt[3]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L13 is error:inst6|cnt[3]~85
--operation mode is arithmetic

F1L13 = CARRY(!F1L11 # !F1_cnt[3]);


--F1L2 is error:inst6|always0~618
--operation mode is normal

F1L2 = F1_cnt[3] & (F1_cnt[7] $ F1_cnt[0]);


--F1L3 is error:inst6|always0~619
--operation mode is normal

F1L3 = !F1_cnt[5] & (F1_cnt[4] & !F1_cnt[2] & !F1_cnt[7] # !F1_cnt[4] & (F1_cnt[7]));


--F1L4 is error:inst6|always0~620
--operation mode is normal

F1L4 = F1L2 & (F1_cnt[1] $ F1L3);


--MC1__clk0 is Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0
MC1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GND), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--P3_q_b[3] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P3_q_b[3]_PORT_A_data_in = G2_out[3];
P3_q_b[3]_PORT_A_data_in_reg = DFFE(P3_q_b[3]_PORT_A_data_in, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[3]_PORT_A_address_reg = DFFE(P3_q_b[3]_PORT_A_address, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[3]_PORT_B_address_reg = DFFE(P3_q_b[3]_PORT_B_address, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[3]_PORT_A_write_enable_reg = DFFE(P3_q_b[3]_PORT_A_write_enable, P3_q_b[3]_clock_0, , , P3_q_b[3]_clock_enable_0);
P3_q_b[3]_PORT_B_read_enable = VCC;
P3_q_b[3]_PORT_B_read_enable_reg = DFFE(P3_q_b[3]_PORT_B_read_enable, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3]_clock_0 = M1_clk_out;
P3_q_b[3]_clock_1 = M5_clk_out;
P3_q_b[3]_clock_enable_0 = H1_wrclocken;
P3_q_b[3]_clock_enable_1 = H1_rdclocken;
P3_q_b[3]_PORT_B_data_out = MEMORY(P3_q_b[3]_PORT_A_data_in_reg, , P3_q_b[3]_PORT_A_address_reg, P3_q_b[3]_PORT_B_address_reg, P3_q_b[3]_PORT_A_write_enable_reg, P3_q_b[3]_PORT_B_read_enable_reg, , , P3_q_b[3]_clock_0, P3_q_b[3]_clock_1, P3_q_b[3]_clock_enable_0, P3_q_b[3]_clock_enable_1, , );
P3_q_b[3]_PORT_B_data_out_reg = DFFE(P3_q_b[3]_PORT_B_data_out, P3_q_b[3]_clock_1, , , P3_q_b[3]_clock_enable_1);
P3_q_b[3] = P3_q_b[3]_PORT_B_data_out_reg[0];


--K1_mem11[1] is RSEncoder:inst|rsenc:D|mem11[1]
--operation mode is normal

K1_mem11[1]_lut_out = K1_mem10[1] $ K1L4 $ K1L3 $ K1L48;
K1_mem11[1] = DFFEAS(K1_mem11[1]_lut_out, M5_clk_out, reset, , , , , , );


--H1_data19 is RSEncoder:inst|fifo_encode:B|data19
--operation mode is normal

H1_data19_lut_out = H1L19 & (!H1L17) # !H1L19 & (H1L18 & (!H1L7 # !H1L17) # !H1L18 & (H1L17 # H1L7));
H1_data19 = DFFEAS(H1_data19_lut_out, M5_clk_out, reset, , H1L6, , , , );


--L2L13 is RSEncoder:inst|Dec2Bit:E|buff~1792
--operation mode is normal

L2L13 = H1_data19 & P3_q_b[3] # !H1_data19 & (K1_mem11[1]);


--L2_buff[3] is RSEncoder:inst|Dec2Bit:E|buff[3]
--operation mode is normal

L2_buff[3]_lut_out = L2L14;
L2_buff[3] = DFFEAS(L2_buff[3]_lut_out, MC1__clk0, VCC, , L2L12, , , , );


--L2_cnt[0] is RSEncoder:inst|Dec2Bit:E|cnt[0]
--operation mode is normal

L2_cnt[0]_lut_out = L2_cnt[2] # !L2_cnt[0];
L2_cnt[0] = DFFEAS(L2_cnt[0]_lut_out, MC1__clk0, reset, , L2_enable, , , , );


--L2_cnt[2] is RSEncoder:inst|Dec2Bit:E|cnt[2]
--operation mode is normal

L2_cnt[2]_lut_out = L2_cnt[2] & (!L2_cnt[0] & !L2_cnt[1]) # !L2_cnt[2] & (L2_cnt[0] & L2_cnt[1]);
L2_cnt[2] = DFFEAS(L2_cnt[2]_lut_out, MC1__clk0, reset, , L2_enable, , , , );


--L2_cnt[1] is RSEncoder:inst|Dec2Bit:E|cnt[1]
--operation mode is normal

L2_cnt[1]_lut_out = !L2_cnt[2] & (L2_cnt[0] $ L2_cnt[1]);
L2_cnt[1] = DFFEAS(L2_cnt[1]_lut_out, MC1__clk0, reset, , L2_enable, , , , );


--L2L1 is RSEncoder:inst|Dec2Bit:E|Equal~149
--operation mode is normal

L2L1 = !L2_cnt[2] & !L2_cnt[1];


--L2L14 is RSEncoder:inst|Dec2Bit:E|buff~1793
--operation mode is normal

L2L14 = L2_cnt[0] & (L2L1 & L2L13 # !L2L1 & (L2_buff[3])) # !L2_cnt[0] & (L2_buff[3]);


--P3_q_b[4] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P3_q_b[4]_PORT_A_data_in = G2_out[4];
P3_q_b[4]_PORT_A_data_in_reg = DFFE(P3_q_b[4]_PORT_A_data_in, P3_q_b[4]_clock_0, , , P3_q_b[4]_clock_enable_0);
P3_q_b[4]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[4]_PORT_A_address_reg = DFFE(P3_q_b[4]_PORT_A_address, P3_q_b[4]_clock_0, , , P3_q_b[4]_clock_enable_0);
P3_q_b[4]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[4]_PORT_B_address_reg = DFFE(P3_q_b[4]_PORT_B_address, P3_q_b[4]_clock_1, , , P3_q_b[4]_clock_enable_1);
P3_q_b[4]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[4]_PORT_A_write_enable_reg = DFFE(P3_q_b[4]_PORT_A_write_enable, P3_q_b[4]_clock_0, , , P3_q_b[4]_clock_enable_0);
P3_q_b[4]_PORT_B_read_enable = VCC;
P3_q_b[4]_PORT_B_read_enable_reg = DFFE(P3_q_b[4]_PORT_B_read_enable, P3_q_b[4]_clock_1, , , P3_q_b[4]_clock_enable_1);
P3_q_b[4]_clock_0 = M1_clk_out;
P3_q_b[4]_clock_1 = M5_clk_out;
P3_q_b[4]_clock_enable_0 = H1_wrclocken;
P3_q_b[4]_clock_enable_1 = H1_rdclocken;
P3_q_b[4]_PORT_B_data_out = MEMORY(P3_q_b[4]_PORT_A_data_in_reg, , P3_q_b[4]_PORT_A_address_reg, P3_q_b[4]_PORT_B_address_reg, P3_q_b[4]_PORT_A_write_enable_reg, P3_q_b[4]_PORT_B_read_enable_reg, , , P3_q_b[4]_clock_0, P3_q_b[4]_clock_1, P3_q_b[4]_clock_enable_0, P3_q_b[4]_clock_enable_1, , );
P3_q_b[4]_PORT_B_data_out_reg = DFFE(P3_q_b[4]_PORT_B_data_out, P3_q_b[4]_clock_1, , , P3_q_b[4]_clock_enable_1);
P3_q_b[4] = P3_q_b[4]_PORT_B_data_out_reg[0];


--K1_mem11[0] is RSEncoder:inst|rsenc:D|mem11[0]
--operation mode is normal

K1_mem11[0]_lut_out = K1L4 $ K1L3 $ K1_mem10[0] $ K1L2;
K1_mem11[0] = DFFEAS(K1_mem11[0]_lut_out, M5_clk_out, reset, , , , , , );


--L2L15 is RSEncoder:inst|Dec2Bit:E|buff~1794
--operation mode is normal

L2L15 = H1_data19 & P3_q_b[4] # !H1_data19 & (K1_mem11[0]);


--L2_buff[4] is RSEncoder:inst|Dec2Bit:E|buff[4]
--operation mode is normal

L2_buff[4]_lut_out = L2L16;
L2_buff[4] = DFFEAS(L2_buff[4]_lut_out, MC1__clk0, VCC, , L2L12, , , , );


--L2L16 is RSEncoder:inst|Dec2Bit:E|buff~1795
--operation mode is normal

L2L16 = L2_cnt[0] & (L2L1 & L2L15 # !L2L1 & (L2_buff[4])) # !L2_cnt[0] & (L2_buff[4]);


--L2L2 is RSEncoder:inst|Dec2Bit:E|Select~343
--operation mode is normal

L2L2 = L2_cnt[1] & (L2_cnt[0]) # !L2_cnt[1] & (L2_cnt[0] & L2L16 # !L2_cnt[0] & (L2_out));


--P3_q_b[2] is RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P3_q_b[2]_PORT_A_data_in = G2_out[2];
P3_q_b[2]_PORT_A_data_in_reg = DFFE(P3_q_b[2]_PORT_A_data_in, P3_q_b[2]_clock_0, , , P3_q_b[2]_clock_enable_0);
P3_q_b[2]_PORT_A_address = BUS(H1_wraddress[0], H1_wraddress[1], H1_wraddress[2], H1_wraddress[3], H1_wraddress[4]);
P3_q_b[2]_PORT_A_address_reg = DFFE(P3_q_b[2]_PORT_A_address, P3_q_b[2]_clock_0, , , P3_q_b[2]_clock_enable_0);
P3_q_b[2]_PORT_B_address = BUS(H1_rdaddress[0], H1_rdaddress[1], H1_rdaddress[2], H1_rdaddress[3], H1_rdaddress[4]);
P3_q_b[2]_PORT_B_address_reg = DFFE(P3_q_b[2]_PORT_B_address, P3_q_b[2]_clock_1, , , P3_q_b[2]_clock_enable_1);
P3_q_b[2]_PORT_A_write_enable = H1_wrclocken;
P3_q_b[2]_PORT_A_write_enable_reg = DFFE(P3_q_b[2]_PORT_A_write_enable, P3_q_b[2]_clock_0, , , P3_q_b[2]_clock_enable_0);
P3_q_b[2]_PORT_B_read_enable = VCC;
P3_q_b[2]_PORT_B_read_enable_reg = DFFE(P3_q_b[2]_PORT_B_read_enable, P3_q_b[2]_clock_1, , , P3_q_b[2]_clock_enable_1);
P3_q_b[2]_clock_0 = M1_clk_out;
P3_q_b[2]_clock_1 = M5_clk_out;
P3_q_b[2]_clock_enable_0 = H1_wrclocken;
P3_q_b[2]_clock_enable_1 = H1_rdclocken;
P3_q_b[2]_PORT_B_data_out = MEMORY(P3_q_b[2]_PORT_A_data_in_reg, , P3_q_b[2]_PORT_A_address_reg, P3_q_b[2]_PORT_B_address_reg, P3_q_b[2]_PORT_A_write_enable_reg, P3_q_b[2]_PORT_B_read_enable_reg, , , P3_q_b[2]_clock_0, P3_q_b[2]_clock_1, P3_q_b[2]_clock_enable_0, P3_q_b[2]_clock_enable_1, , );
P3_q_b[2]_PORT_B_data_out_reg = DFFE(P3_q_b[2]_PORT_B_data_out, P3_q_b[2]_clock_1, , , P3_q_b[2]_clock_enable_1);
P3_q_b[2] = P3_q_b[2]_PORT_B_data_out_reg[0];


--K1_mem11[2] is RSEncoder:inst|rsenc:D|mem11[2]
--operation mode is normal

K1_mem11[2]_lut_out = K1L3 $ K1L5 $ K1L1 $ K1_mem10[2];
K1_mem11[2] = DFFEAS(K1_mem11[2]_lut_out, M5_clk_out, reset, , , , , , );


--L2L17 is RSEncoder:inst|Dec2Bit:E|buff~1796
--operation mode is normal

L2L17 = H1_data19 & P3_q_b[2] # !H1_data19 & (K1_mem11[2]);


--L2_buff[2] is RSEncoder:inst|Dec2Bit:E|buff[2]
--operation mode is normal

L2_buff[2]_lut_out = L2L18;
L2_buff[2] = DFFEAS(L2_buff[2]_lut_out, MC1__clk0, VCC, , L2L12, , , , );


--L2L18 is RSEncoder:inst|Dec2Bit:E|buff~1797
--operation mode is normal

L2L18 = L2_cnt[0] & (L2L1 & L2L17 # !L2L1 & (L2_buff[2])) # !L2_cnt[0] & (L2_buff[2]);


--L2L3 is RSEncoder:inst|Dec2Bit:E|Select~344
--operation mode is normal

L2L3 = L2_cnt[1] & (L2L2 & (L2L18) # !L2L2 & L2L14) # !L2_cnt[1] & (L2L2);


--L2L4 is RSEncoder:inst|Dec2Bit:E|Select~345
--operation mode is normal

L2L4 = L2_out & L2_cnt[1];


--L2_buff[0] is RSEncoder:inst|Dec2Bit:E|buff[0]
--operation mode is normal

L2_buff[0]_lut_out = L2_cnt[0] & (L2L1 & L2L19 # !L2L1 & (L2_buff[0])) # !L2_cnt[0] & (L2_buff[0]);
L2_buff[0] = DFFEAS(L2_buff[0]_lut_out, MC1__clk0, VCC, , L2L12, , , , );


--L2_buff[1] is RSEncoder:inst|Dec2Bit:E|buff[1]
--operation mode is normal

L2_buff[1]_lut_out = L2_cnt[0] & (L2L1 & L2L20 # !L2L1 & (L2_buff[1])) # !L2_cnt[0] & (L2_buff[1]);
L2_buff[1] = DFFEAS(L2_buff[1]_lut_out, MC1__clk0, VCC, , L2L12, , , , );


--L2L5 is RSEncoder:inst|Dec2Bit:E|Select~346
--operation mode is normal

L2L5 = !L2_cnt[1] & (L2_cnt[0] & L2_buff[0] # !L2_cnt[0] & (L2_buff[1]));


--L2_enable is RSEncoder:inst|Dec2Bit:E|enable
--operation mode is normal

L2_enable_lut_out = VCC;
L2_enable = DFFEAS(L2_enable_lut_out, !H1_wordstart, reset, , , , , , );


--P2_q_b[0] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P2_q_b[0]_PORT_A_data_in = X13_out[4];
P2_q_b[0]_PORT_A_data_in_reg = DFFE(P2_q_b[0]_PORT_A_data_in, P2_q_b[0]_clock_0, , , P2_q_b[0]_clock_enable_0);
P2_q_b[0]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[0]_PORT_A_address_reg = DFFE(P2_q_b[0]_PORT_A_address, P2_q_b[0]_clock_0, , , P2_q_b[0]_clock_enable_0);
P2_q_b[0]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[0]_PORT_B_address_reg = DFFE(P2_q_b[0]_PORT_B_address, P2_q_b[0]_clock_1, , , P2_q_b[0]_clock_enable_1);
P2_q_b[0]_PORT_A_write_enable = S1_wren;
P2_q_b[0]_PORT_A_write_enable_reg = DFFE(P2_q_b[0]_PORT_A_write_enable, P2_q_b[0]_clock_0, , , P2_q_b[0]_clock_enable_0);
P2_q_b[0]_PORT_B_read_enable = VCC;
P2_q_b[0]_PORT_B_read_enable_reg = DFFE(P2_q_b[0]_PORT_B_read_enable, P2_q_b[0]_clock_1, , , P2_q_b[0]_clock_enable_1);
P2_q_b[0]_clock_0 = M3_clk_out;
P2_q_b[0]_clock_1 = M1_clk_out;
P2_q_b[0]_clock_enable_0 = S1_wrclocken;
P2_q_b[0]_clock_enable_1 = S1_rdclocken;
P2_q_b[0]_PORT_B_data_out = MEMORY(P2_q_b[0]_PORT_A_data_in_reg, , P2_q_b[0]_PORT_A_address_reg, P2_q_b[0]_PORT_B_address_reg, P2_q_b[0]_PORT_A_write_enable_reg, P2_q_b[0]_PORT_B_read_enable_reg, , , P2_q_b[0]_clock_0, P2_q_b[0]_clock_1, P2_q_b[0]_clock_enable_0, P2_q_b[0]_clock_enable_1, , );
P2_q_b[0]_PORT_B_data_out_reg = DFFE(P2_q_b[0]_PORT_B_data_out, P2_q_b[0]_clock_1, , , P2_q_b[0]_clock_enable_1);
P2_q_b[0] = P2_