top.map.eqn

RS编码的verilog源代码

--SB17_out[3] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[3]
--operation mode is normal

SB17_out[3]_lut_out = MB9_outadder[3];
SB17_out[3] = DFFEAS(SB17_out[3]_lut_out, M3_clk_out, VCC, , QB1_hold, JC9_out[3], , SB9L7, QB1_state.st1);


--RB1L2 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out[0]~422
--operation mode is normal

RB1L2 = RB1L1 & !SB17_out[2] & !SB17_out[0] & !SB17_out[3];


--SB19_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE9|register_pe:reg1|out[4]
--operation mode is normal

SB19_out[4]_lut_out = MB10_outadder[4];
SB19_out[4] = DFFEAS(SB19_out[4]_lut_out, M3_clk_out, VCC, , QB1_hold, JC10_out[4], , SB9L7, QB1_state.st1);


--SB19_out[1] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE9|register_pe:reg1|out[1]
--operation mode is normal

SB19_out[1]_lut_out = MB10_outadder[1];
SB19_out[1] = DFFEAS(SB19_out[1]_lut_out, M3_clk_out, VCC, , QB1_hold, JC10_out[1], , SB9L7, QB1_state.st1);


--RB1L5 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out~423
--operation mode is normal

RB1L5 = !SB19_out[4] & !SB19_out[1];


--SB19_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE9|register_pe:reg1|out[2]
--operation mode is normal

SB19_out[2]_lut_out = MB10L27;
SB19_out[2] = DFFEAS(SB19_out[2]_lut_out, M3_clk_out, VCC, , QB1_hold, JC10_out[2], , SB9L7, QB1_state.st1);


--SB19_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE9|register_pe:reg1|out[0]
--operation mode is normal

SB19_out[0]_lut_out = MB10_outadder[0];
SB19_out[0] = DFFEAS(SB19_out[0]_lut_out, M3_clk_out, VCC, , QB1_hold, JC10_out[0], , SB9L7, QB1_state.st1);


--SB19_out[3] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE9|register_pe:reg1|out[3]
--operation mode is normal

SB19_out[3]_lut_out = MB10_outadder[3];
SB19_out[3] = DFFEAS(SB19_out[3]_lut_out, M3_clk_out, VCC, , QB1_hold, JC10_out[3], , SB9L7, QB1_state.st1);


--RB1L6 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out~424
--operation mode is normal

RB1L6 = RB1L5 & !SB19_out[2] & !SB19_out[0] & !SB19_out[3];


--SB23_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE11|register_pe:reg1|out[2]
--operation mode is normal

SB23_out[2]_lut_out = MB12L27;
SB23_out[2] = DFFEAS(SB23_out[2]_lut_out, M3_clk_out, VCC, , QB1_hold, JC12_out[2], , SB9L7, QB1_state.st1);


--SB23_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE11|register_pe:reg1|out[0]
--operation mode is normal

SB23_out[0]_lut_out = MB12_outadder[0];
SB23_out[0] = DFFEAS(SB23_out[0]_lut_out, M3_clk_out, VCC, , QB1_hold, JC12_out[0], , SB9L7, QB1_state.st1);


--SB23_out[3] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE11|register_pe:reg1|out[3]
--operation mode is normal

SB23_out[3]_lut_out = MB12_outadder[3];
SB23_out[3] = DFFEAS(SB23_out[3]_lut_out, M3_clk_out, VCC, , QB1_hold, JC12_out[3], , SB9L7, QB1_state.st1);


--SB23_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE11|register_pe:reg1|out[4]
--operation mode is normal

SB23_out[4]_lut_out = MB12_outadder[4];
SB23_out[4] = DFFEAS(SB23_out[4]_lut_out, M3_clk_out, VCC, , QB1_hold, JC12_out[4], , SB9L7, QB1_state.st1);


--SB23_out[1] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE11|register_pe:reg1|out[1]
--operation mode is normal

SB23_out[1]_lut_out = MB12_outadder[1];
SB23_out[1] = DFFEAS(SB23_out[1]_lut_out, M3_clk_out, VCC, , QB1_hold, JC12_out[1], , SB9L7, QB1_state.st1);


--V1L5 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp5~36
--operation mode is normal

V1L5 = SB23_out[4] # SB23_out[1];


--V1_koefcomp5 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp5
--operation mode is normal

V1_koefcomp5 = SB23_out[2] # SB23_out[0] # SB23_out[3] # V1L5;


--SB21_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE10|register_pe:reg1|out[2]
--operation mode is normal

SB21_out[2]_lut_out = MB11L27;
SB21_out[2] = DFFEAS(SB21_out[2]_lut_out, M3_clk_out, VCC, , QB1_hold, JC11_out[2], , SB9L7, QB1_state.st1);


--SB21_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE10|register_pe:reg1|out[0]
--operation mode is normal

SB21_out[0]_lut_out = MB11_outadder[0];
SB21_out[0] = DFFEAS(SB21_out[0]_lut_out, M3_clk_out, VCC, , QB1_hold, JC11_out[0], , SB9L7, QB1_state.st1);


--SB21_out[3] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE10|register_pe:reg1|out[3]
--operation mode is normal

SB21_out[3]_lut_out = MB11_outadder[3];
SB21_out[3] = DFFEAS(SB21_out[3]_lut_out, M3_clk_out, VCC, , QB1_hold, JC11_out[3], , SB9L7, QB1_state.st1);


--SB21_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE10|register_pe:reg1|out[4]
--operation mode is normal

SB21_out[4]_lut_out = MB11_outadder[4];
SB21_out[4] = DFFEAS(SB21_out[4]_lut_out, M3_clk_out, VCC, , QB1_hold, JC11_out[4], , SB9L7, QB1_state.st1);


--SB21_out[1] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE10|register_pe:reg1|out[1]
--operation mode is normal

SB21_out[1]_lut_out = MB11_outadder[1];
SB21_out[1] = DFFEAS(SB21_out[1]_lut_out, M3_clk_out, VCC, , QB1_hold, JC11_out[1], , SB9L7, QB1_state.st1);


--V1L3 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp4~34
--operation mode is normal

V1L3 = SB21_out[4] # SB21_out[1];


--V1_koefcomp4 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp4
--operation mode is normal

V1_koefcomp4 = SB21_out[2] # SB21_out[0] # SB21_out[3] # V1L3;


--RB1L7 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out~425
--operation mode is normal

RB1L7 = !V1_koefcomp5 & !V1_koefcomp4 & (!RB1L6 # !RB1L2);


--U1_rootcntr[2] is RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|rootcntr[2]
--operation mode is normal

U1_rootcntr[2]_lut_out = U1_rootcntr[2] $ (U1_rootcntr[1] & U1_rootcntr[0] & !U1L32);
U1_rootcntr[2] = DFFEAS(U1_rootcntr[2]_lut_out, !M3_clk_out, VCC, , , , , !U1_state, );


--Y1L1 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|Equal~311
--operation mode is normal

Y1L1 = U1_rootcntr[2] $ (V1_koefcomp6 # V1_koefcomp5 # V1_koefcomp4);


--Y1L2 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|Equal~312
--operation mode is normal

Y1L2 = !Y1L1 & (U1_rootcntr[1] $ (!V1_koefcomp6 & !RB1L7));


--U1_rootcntr[0] is RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|rootcntr[0]
--operation mode is normal

U1_rootcntr[0]_lut_out = U1_rootcntr[0] $ !U1L32;
U1_rootcntr[0] = DFFEAS(U1_rootcntr[0]_lut_out, !M3_clk_out, VCC, , , , , !U1_state, );


--SB15_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE7|register_pe:reg1|out[2]
--operation mode is normal

SB15_out[2]_lut_out = MB8L27;
SB15_out[2] = DFFEAS(SB15_out[2]_lut_out, M3_clk_out, VCC, , QB1_hold, JC8_out[2], , SB9L7, QB1_state.st1);


--SB15_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE7|register_pe:reg1|out[4]
--operation mode is normal

SB15_out[4]_lut_out = MB8_outadder[4];
SB15_out[4] = DFFEAS(SB15_out[4]_lut_out, M3_clk_out, VCC, , QB1_hold, JC8_out[4], , SB9L7, QB1_state.st1);


--SB15_out[1] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE7|register_pe:reg1|out[1]
--operation mode is normal

SB15_out[1]_lut_out = MB8_outadder[1];
SB15_out[1] = DFFEAS(SB15_out[1]_lut_out, M3_clk_out, VCC, , QB1_hold, JC8_out[1], , SB9L7, QB1_state.st1);


--SB15_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE7|register_pe:reg1|out[0]
--operation mode is normal

SB15_out[0]_lut_out = MB8_outadder[0];
SB15_out[0] = DFFEAS(SB15_out[0]_lut_out, M3_clk_out, VCC, , QB1_hold, JC8_out[0], , SB9L7, QB1_state.st1);


--SB15_out[3] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE7|register_pe:reg1|out[3]
--operation mode is normal

SB15_out[3]_lut_out = MB8_outadder[3];
SB15_out[3] = DFFEAS(SB15_out[3]_lut_out, M3_clk_out, VCC, , QB1_hold, JC8_out[3], , SB9L7, QB1_state.st1);


--V1L1 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp1~27
--operation mode is normal

V1L1 = SB15_out[4] # SB15_out[1] # SB15_out[0] # SB15_out[3];


--RB1L3 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out[0]~426
--operation mode is normal

RB1L3 = RB1L2 & (SB15_out[2] # V1L1) # !RB1L6;


--RB1L4 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out[0]~427
--operation mode is normal

RB1L4 = !V1_koefcomp6 & (V1_koefcomp5 # RB1L3 & !V1_koefcomp4);


--Y1L3 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|Equal~313
--operation mode is normal

Y1L3 = Y1L2 & (U1_rootcntr[0] $ !RB1L4);


--Y1_state1.st1_7 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_7
--operation mode is normal

Y1_state1.st1_7_lut_out = Y1_state1.st1_6 # Y1_state1.st1_7 & !Y1L44 & !R1_wordstart;
Y1_state1.st1_7 = DFFEAS(Y1_state1.st1_7_lut_out, M3_clk_out, reset, , , , , , );


--D1_c5 is nrz:inst2|c5
--operation mode is normal

D1_c5_lut_out = D1_c4;
D1_c5 = DFFEAS(D1_c5_lut_out, KC1_clk_out, VCC, , reset, , , , );


--D1_cnt[1] is nrz:inst2|cnt[1]
--operation mode is normal

D1_cnt[1]_lut_out = D1_cnt[1] $ D1_cnt[0];
D1_cnt[1] = DFFEAS(D1_cnt[1]_lut_out, KC1_clk_out, reset, , , , , , );


--D1_cnt[0] is nrz:inst2|cnt[0]
--operation mode is normal

D1_cnt[0]_lut_out = D1_cnt[2] & D1_cnt[1] # !D1_cnt[0];
D1_cnt[0] = DFFEAS(D1_cnt[0]_lut_out, KC1_clk_out, reset, , , , , , );


--D1_cnt[2] is nrz:inst2|cnt[2]
--operation mode is normal

D1_cnt[2]_lut_out = D1_cnt[2] # D1_cnt[1] & D1_cnt[0];
D1_cnt[2] = DFFEAS(D1_cnt[2]_lut_out, KC1_clk_out, reset, , , , , , );


--F1_cnt[6] is error:inst6|cnt[6]
--operation mode is arithmetic

F1_cnt[6]_carry_eqn = F1L17;
F1_cnt[6]_lut_out = F1_cnt[6] $ (!F1_cnt[6]_carry_eqn);
F1_cnt[6] = DFFEAS(F1_cnt[6]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L19 is error:inst6|cnt[6]~57
--operation mode is arithmetic

F1L19 = CARRY(F1_cnt[6] & (!F1L17));


--F1_cnt[4] is error:inst6|cnt[4]
--operation mode is arithmetic

F1_cnt[4]_carry_eqn = F1L13;
F1_cnt[4]_lut_out = F1_cnt[4] $ (!F1_cnt[4]_carry_eqn);
F1_cnt[4] = DFFEAS(F1_cnt[4]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L15 is error:inst6|cnt[4]~61
--operation mode is arithmetic

F1L15 = CARRY(F1_cnt[4] & (!F1L13));


--F1_cnt[5] is error:inst6|cnt[5]
--operation mode is arithmetic

F1_cnt[5]_carry_eqn = F1L15;
F1_cnt[5]_lut_out = F1_cnt[5] $ (F1_cnt[5]_carry_eqn);
F1_cnt[5] = DFFEAS(F1_cnt[5]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L17 is error:inst6|cnt[5]~65
--operation mode is arithmetic

F1L17 = CARRY(!F1L15 # !F1_cnt[5]);


--F1_cnt[2] is error:inst6|cnt[2]
--operation mode is arithmetic

F1_cnt[2]_carry_eqn = F1L9;
F1_cnt[2]_lut_out = F1_cnt[2] $ (!F1_cnt[2]_carry_eqn);
F1_cnt[2] = DFFEAS(F1_cnt[2]_lut_out, MC1__clk0, VCC, , , , , , );

--F1L11 is error:inst6|cnt[2]~69
--operation mode is arithmetic