top.map.eqn

RS编码的verilog源代码

JC9_out[3] = DFFEAS(JC9_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC9_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[2]
--operation mode is normal

JC9_out[2]_lut_out = JC9_out[3] $ P1_q_b[2];
JC9_out[2] = DFFEAS(JC9_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC9_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[1]
--operation mode is normal

JC9_out[1]_lut_out = JC9_out[2] $ JC9_out[4] $ (P1_q_b[1]);
JC9_out[1] = DFFEAS(JC9_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC9_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[0]
--operation mode is normal

JC9_out[0]_lut_out = JC9_out[3] $ JC9_out[1] $ (P1_q_b[0]);
JC9_out[0] = DFFEAS(JC9_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L13 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~785
--operation mode is normal

W1L13 = JC9_out[3] # JC9_out[2] # JC9_out[1] # JC9_out[0];


--JC9_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[4]
--operation mode is normal

JC9_out[4]_lut_out = JC9_out[2] $ JC9_out[0] $ JC9_out[4] $ P1_q_b[4];
JC9_out[4] = DFFEAS(JC9_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC10_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[3]
--operation mode is normal

JC10_out[3]_lut_out = JC10_out[2] $ JC10_out[0] $ JC10_out[4] $ P1_q_b[3];
JC10_out[3] = DFFEAS(JC10_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC10_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[2]
--operation mode is normal

JC10_out[2]_lut_out = JC10_out[4] $ P1_q_b[2];
JC10_out[2] = DFFEAS(JC10_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC10_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[1]
--operation mode is normal

JC10_out[1]_lut_out = JC10_out[3] $ P1_q_b[1];
JC10_out[1] = DFFEAS(JC10_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L14 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~786
--operation mode is normal

W1L14 = JC9_out[4] # JC10_out[3] # JC10_out[2] # JC10_out[1];


--W1L15 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~787
--operation mode is normal

W1L15 = W1L11 # W1L12 # W1L13 # W1L14;


--JC10_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[0]
--operation mode is normal

JC10_out[0]_lut_out = JC10_out[2] $ JC10_out[4] $ (P1_q_b[0]);
JC10_out[0] = DFFEAS(JC10_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC10_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit|out[4]
--operation mode is normal

JC10_out[4]_lut_out = JC10_out[3] $ JC10_out[1] $ (P1_q_b[4]);
JC10_out[4] = DFFEAS(JC10_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC11_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[3]
--operation mode is normal

JC11_out[3]_lut_out = JC11_out[3] $ JC11_out[1] $ (P1_q_b[3]);
JC11_out[3] = DFFEAS(JC11_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC11_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[2]
--operation mode is normal

JC11_out[2]_lut_out = JC11_out[0] $ P1_q_b[2];
JC11_out[2] = DFFEAS(JC11_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L16 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~788
--operation mode is normal

W1L16 = JC10_out[0] # JC10_out[4] # JC11_out[3] # JC11_out[2];


--JC11_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[1]
--operation mode is normal

JC11_out[1]_lut_out = JC11_out[4] $ P1_q_b[1];
JC11_out[1] = DFFEAS(JC11_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC11_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[0]
--operation mode is normal

JC11_out[0]_lut_out = JC11_out[3] $ P1_q_b[0];
JC11_out[0] = DFFEAS(JC11_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC11_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit|out[4]
--operation mode is normal

JC11_out[4]_lut_out = JC11_out[2] $ JC11_out[4] $ (P1_q_b[4]);
JC11_out[4] = DFFEAS(JC11_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC12_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[3]
--operation mode is normal

JC12_out[3]_lut_out = JC12_out[2] $ JC12_out[4] $ (P1_q_b[3]);
JC12_out[3] = DFFEAS(JC12_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L17 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~789
--operation mode is normal

W1L17 = JC11_out[1] # JC11_out[0] # JC11_out[4] # JC12_out[3];


--JC12_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[2]
--operation mode is normal

JC12_out[2]_lut_out = JC12_out[1] $ P1_q_b[2];
JC12_out[2] = DFFEAS(JC12_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC12_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[1]
--operation mode is normal

JC12_out[1]_lut_out = JC12_out[0] $ P1_q_b[1];
JC12_out[1] = DFFEAS(JC12_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC12_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[0]
--operation mode is normal

JC12_out[0]_lut_out = JC12_out[4] $ P1_q_b[0];
JC12_out[0] = DFFEAS(JC12_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC12_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit|out[4]
--operation mode is normal

JC12_out[4]_lut_out = JC12_out[3] $ P1_q_b[4];
JC12_out[4] = DFFEAS(JC12_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L18 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~790
--operation mode is normal

W1L18 = JC12_out[2] # JC12_out[1] # JC12_out[0] # JC12_out[4];


--W1L19 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~791
--operation mode is normal

W1L19 = W1L15 # W1L16 # W1L17 # W1L18;


--Y1L39 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|nxt_state1.st1_4~10
--operation mode is normal

Y1L39 = W1_state.st2 & (W1L5 # W1L10 # W1L19);


--M3_clk_temp1 is RSDecoder:inst1|divide5:dividec|clk_temp1
--operation mode is normal

M3_clk_temp1_lut_out = M3_clk_temp1 $ (!M3_counter[0] & (M3_counter[2] $ M3_counter[1]));
M3_clk_temp1 = DFFEAS(M3_clk_temp1_lut_out, clk, VCC, , , , , , );


--M3_clk_temp2 is RSDecoder:inst1|divide5:dividec|clk_temp2
--operation mode is normal

M3_clk_temp2_lut_out = M3_clk_temp1;
M3_clk_temp2 = DFFEAS(M3_clk_temp2_lut_out, !clk, VCC, , , , , , );


--M3_clk_out is RSDecoder:inst1|divide5:dividec|clk_out
--operation mode is normal

M3_clk_out = M3_clk_temp1 # M3_clk_temp2;


--Y1_state2.st2_10 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_10
--operation mode is normal

Y1_state2.st2_10_lut_out = Y1L5 & Y1_state2.st2_9 & (!Y1_lastdataout);
Y1_state2.st2_10 = DFFEAS(Y1_state2.st2_10_lut_out, !M3_clk_out, reset, , , , , , );


--Y1_state2.st2_7 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_7
--operation mode is normal

Y1_state2.st2_7_lut_out = Y1_state2.st2_6 & Y1L8 & (!Y1_lastdataout);
Y1_state2.st2_7 = DFFEAS(Y1_state2.st2_7_lut_out, !M3_clk_out, reset, , , , , , );


--Y1_state2.st2_11 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state2.st2_11
--operation mode is normal

Y1_state2.st2_11_lut_out = Y1_state2.st2_9 & (!Y1L5 & !Y1_lastdataout);
Y1_state2.st2_11 = DFFEAS(Y1_state2.st2_11_lut_out, !M3_clk_out, reset, , , , , , );


--Y1L44 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|reduce_or~82
--operation mode is normal

Y1L44 = Y1_state2.st2_10 # Y1_state2.st2_7 # Y1_state2.st2_11;


--Y1_state1.st1_9 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_9
--operation mode is normal

Y1_state1.st1_9_lut_out = !Y1L44 & (Y1_state1.st1_9 # Y1_state1.st1_8);
Y1_state1.st1_9 = DFFEAS(Y1_state1.st1_9_lut_out, M3_clk_out, reset, , , , , , );


--Y1_state1.st1_8 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_8
--operation mode is normal

Y1_state1.st1_8_lut_out = Y1_state1.st1_7 & R1_wordstart & (!Y1L44);
Y1_state1.st1_8 = DFFEAS(Y1_state1.st1_8_lut_out, M3_clk_out, reset, , , , , , );


--U1_rootcntr[1] is RSDecoder:inst1|rsdec:rsdec|CSEEblock:CSEEblock|rootcntr[1]
--operation mode is normal

U1_rootcntr[1]_lut_out = U1_rootcntr[1] $ (U1_rootcntr[0] & (!U1L32));
U1_rootcntr[1] = DFFEAS(U1_rootcntr[1]_lut_out, !M3_clk_out, VCC, , , , , !U1_state, );


--SB25_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12|register_pe:reg1|out[2]
--operation mode is normal

SB25_out[2]_lut_out = NB1L22;
SB25_out[2] = DFFEAS(SB25_out[2]_lut_out, M3_clk_out, VCC, , QB1_hold, , , !QB1_state.st2, );


--SB25_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12|register_pe:reg1|out[0]
--operation mode is normal

SB25_out[0]_lut_out = NB1_outadder[0];
SB25_out[0] = DFFEAS(SB25_out[0]_lut_out, M3_clk_out, VCC, , QB1_hold, , , !QB1_state.st2, );


--SB25_out[3] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12|register_pe:reg1|out[3]
--operation mode is normal

SB25_out[3]_lut_out = NB1_outadder[3];
SB25_out[3] = DFFEAS(SB25_out[3]_lut_out, M3_clk_out, VCC, , QB1_hold, , , !QB1_state.st2, );


--SB25_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12|register_pe:reg1|out[4]
--operation mode is normal

SB25_out[4]_lut_out = KB26L5 $ KB26_intvald[0] $ KB25L5 $ KB25_intvald[0];
SB25_out[4] = DFFEAS(SB25_out[4]_lut_out, M3_clk_out, VCC, , QB1_hold, , , !QB1_state.st2, );


--SB25_out[1] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE_12:PE12|register_pe:reg1|out[1]
--operation mode is normal

SB25_out[1]_lut_out = NB1L15;
SB25_out[1] = DFFEAS(SB25_out[1]_lut_out, M3_clk_out, VCC, , QB1_hold, , , !QB1_state.st2, );


--V1L7 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp6~41
--operation mode is normal

V1L7 = SB25_out[4] # SB25_out[1];


--V1_koefcomp6 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|koefcomp6
--operation mode is normal

V1_koefcomp6 = SB25_out[2] # SB25_out[0] # SB25_out[3] # V1L7;


--SB17_out[4] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[4]
--operation mode is normal

SB17_out[4]_lut_out = MB9_outadder[4];
SB17_out[4] = DFFEAS(SB17_out[4]_lut_out, M3_clk_out, VCC, , QB1_hold, JC9_out[4], , SB9L7, QB1_state.st1);


--SB17_out[1] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[1]
--operation mode is normal

SB17_out[1]_lut_out = MB9_outadder[1];
SB17_out[1] = DFFEAS(SB17_out[1]_lut_out, M3_clk_out, VCC, , QB1_hold, JC9_out[1], , SB9L7, QB1_state.st1);


--RB1L1 is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|priority_encoder:pencoder|out[0]~421
--operation mode is normal

RB1L1 = !SB17_out[4] & !SB17_out[1];


--SB17_out[2] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[2]
--operation mode is normal

SB17_out[2]_lut_out = MB9L27;
SB17_out[2] = DFFEAS(SB17_out[2]_lut_out, M3_clk_out, VCC, , QB1_hold, JC9_out[2], , SB9L7, QB1_state.st1);


--SB17_out[0] is RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE8|register_pe:reg1|out[0]
--operation mode is normal

SB17_out[0]_lut_out = MB9_outadder[0];
SB17_out[0] = DFFEAS(SB17_out[0]_lut_out, M3_clk_out, VCC, , QB1_hold, JC9_out[0], , SB9L7, QB1_state.st1);