top.map.eqn

RS编码的verilog源代码

JC1_out[0] = DFFEAS(JC1_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L1 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~773
--operation mode is normal

W1L1 = JC1_out[3] # JC1_out[2] # JC1_out[1] # JC1_out[0];


--JC1_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[4]
--operation mode is normal

JC1_out[4]_lut_out = JC1_out[1] $ JC1_out[0] $ (P1_q_b[4]);
JC1_out[4] = DFFEAS(JC1_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC2_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[3]
--operation mode is normal

JC2_out[3]_lut_out = JC2_out[1] $ JC2_out[0] $ (P1_q_b[3]);
JC2_out[3] = DFFEAS(JC2_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC2_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[2]
--operation mode is normal

JC2_out[2]_lut_out = X2_out[2];
JC2_out[2] = DFFEAS(JC2_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC2_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[1]
--operation mode is normal

JC2_out[1]_lut_out = X2_out[3];
JC2_out[1] = DFFEAS(JC2_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L2 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~774
--operation mode is normal

W1L2 = JC1_out[4] # JC2_out[3] # JC2_out[2] # JC2_out[1];


--JC2_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[0]
--operation mode is normal

JC2_out[0]_lut_out = JC2_out[3] $ JC2_out[2] $ JC2_out[0] $ P1_q_b[0];
JC2_out[0] = DFFEAS(JC2_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC2_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit|out[4]
--operation mode is normal

JC2_out[4]_lut_out = JC2_out[2] $ JC2_out[1] $ (P1_q_b[4]);
JC2_out[4] = DFFEAS(JC2_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC3_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[3]
--operation mode is normal

JC3_out[3]_lut_out = JC3_out[2] $ JC3_out[1] $ (P1_q_b[3]);
JC3_out[3] = DFFEAS(JC3_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC3_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[2]
--operation mode is normal

JC3_out[2]_lut_out = JC3_out[3] $ JC3_out[2] $ JC3_out[1] $ P1_q_b[2];
JC3_out[2] = DFFEAS(JC3_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L3 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~775
--operation mode is normal

W1L3 = JC2_out[0] # JC2_out[4] # JC3_out[3] # JC3_out[2];


--JC3_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[1]
--operation mode is normal

JC3_out[1]_lut_out = X3_out[3];
JC3_out[1] = DFFEAS(JC3_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC3_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[0]
--operation mode is normal

JC3_out[0]_lut_out = X3_out[4];
JC3_out[0] = DFFEAS(JC3_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC3_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit|out[4]
--operation mode is normal

JC3_out[4]_lut_out = JC3_out[3] $ JC3_out[2] $ JC3_out[0] $ P1_q_b[4];
JC3_out[4] = DFFEAS(JC3_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC4_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[3]
--operation mode is normal

JC4_out[3]_lut_out = JC4_out[3] $ JC4_out[2] $ JC4_out[0] $ P1_q_b[3];
JC4_out[3] = DFFEAS(JC4_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L4 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~776
--operation mode is normal

W1L4 = JC3_out[1] # JC3_out[0] # JC3_out[4] # JC4_out[3];


--W1L5 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~777
--operation mode is normal

W1L5 = W1L1 # W1L2 # W1L3 # W1L4;


--JC4_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[2]
--operation mode is normal

JC4_out[2]_lut_out = X4_out[2];
JC4_out[2] = DFFEAS(JC4_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC4_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[1]
--operation mode is normal

JC4_out[1]_lut_out = JC4_out[3] $ JC4_out[2] $ JC4_out[1] $ P1_q_b[1];
JC4_out[1] = DFFEAS(JC4_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC4_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[0]
--operation mode is normal

JC4_out[0]_lut_out = X4_out[4];
JC4_out[0] = DFFEAS(JC4_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC4_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit|out[4]
--operation mode is normal

JC4_out[4]_lut_out = X4_out[0];
JC4_out[4] = DFFEAS(JC4_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L6 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~778
--operation mode is normal

W1L6 = JC4_out[2] # JC4_out[1] # JC4_out[0] # JC4_out[4];


--JC5_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[3]
--operation mode is normal

JC5_out[3]_lut_out = X5_out[1];
JC5_out[3] = DFFEAS(JC5_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC5_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[2]
--operation mode is normal

JC5_out[2]_lut_out = JC5_out[3] $ JC5_out[1] $ JC5_out[4] $ P1_q_b[2];
JC5_out[2] = DFFEAS(JC5_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC5_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[1]
--operation mode is normal

JC5_out[1]_lut_out = X5_out[3];
JC5_out[1] = DFFEAS(JC5_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC5_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[0]
--operation mode is normal

JC5_out[0]_lut_out = JC5_out[3] $ JC5_out[2] $ JC5_out[1] $ P1_q_b[0];
JC5_out[0] = DFFEAS(JC5_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L7 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~779
--operation mode is normal

W1L7 = JC5_out[3] # JC5_out[2] # JC5_out[1] # JC5_out[0];


--JC5_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit|out[4]
--operation mode is normal

JC5_out[4]_lut_out = X5_out[0];
JC5_out[4] = DFFEAS(JC5_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC6_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[3]
--operation mode is normal

JC6_out[3]_lut_out = X6_out[1];
JC6_out[3] = DFFEAS(JC6_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC6_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[2]
--operation mode is normal

JC6_out[2]_lut_out = JC6_out[2] $ JC6_out[0] $ JC6_out[4] $ P1_q_b[2];
JC6_out[2] = DFFEAS(JC6_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC6_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[1]
--operation mode is normal

JC6_out[1]_lut_out = JC6_out[3] $ JC6_out[1] $ JC6_out[4] $ P1_q_b[1];
JC6_out[1] = DFFEAS(JC6_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L8 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~780
--operation mode is normal

W1L8 = JC5_out[4] # JC6_out[3] # JC6_out[2] # JC6_out[1];


--JC6_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[0]
--operation mode is normal

JC6_out[0]_lut_out = X6_out[4];
JC6_out[0] = DFFEAS(JC6_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC6_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit|out[4]
--operation mode is normal

JC6_out[4]_lut_out = JC6_out[3] $ JC6_out[2] $ JC6_out[1] $ P1_q_b[4];
JC6_out[4] = DFFEAS(JC6_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC7_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[3]
--operation mode is normal

JC7_out[3]_lut_out = JC7_out[3] $ JC7_out[2] $ JC7_out[1] $ P1_q_b[3];
JC7_out[3] = DFFEAS(JC7_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC7_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[2]
--operation mode is normal

JC7_out[2]_lut_out = JC7_out[3] $ JC7_out[1] $ (P1_q_b[2]);
JC7_out[2] = DFFEAS(JC7_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L9 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~781
--operation mode is normal

W1L9 = JC6_out[0] # JC6_out[4] # JC7_out[3] # JC7_out[2];


--W1L10 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~782
--operation mode is normal

W1L10 = W1L6 # W1L7 # W1L8 # W1L9;


--JC7_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[1]
--operation mode is normal

JC7_out[1]_lut_out = JC7_out[2] $ JC7_out[0] $ JC7_out[4] $ P1_q_b[1];
JC7_out[1] = DFFEAS(JC7_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC7_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[0]
--operation mode is normal

JC7_out[0]_lut_out = JC7_out[3] $ JC7_out[1] $ JC7_out[4] $ P1_q_b[0];
JC7_out[0] = DFFEAS(JC7_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC7_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit|out[4]
--operation mode is normal

JC7_out[4]_lut_out = X7_out[0];
JC7_out[4] = DFFEAS(JC7_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC8_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[3]
--operation mode is normal

JC8_out[3]_lut_out = X8_out[1];
JC8_out[3] = DFFEAS(JC8_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L11 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~783
--operation mode is normal

W1L11 = JC7_out[1] # JC7_out[0] # JC7_out[4] # JC8_out[3];


--JC8_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[2]
--operation mode is normal

JC8_out[2]_lut_out = JC8_out[2] $ JC8_out[4] $ (P1_q_b[2]);
JC8_out[2] = DFFEAS(JC8_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC8_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[1]
--operation mode is normal

JC8_out[1]_lut_out = JC8_out[3] $ JC8_out[1] $ (P1_q_b[1]);
JC8_out[1] = DFFEAS(JC8_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC8_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[0]
--operation mode is normal

JC8_out[0]_lut_out = JC8_out[2] $ JC8_out[0] $ JC8_out[4] $ P1_q_b[0];
JC8_out[0] = DFFEAS(JC8_out[0]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC8_out[4] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit|out[4]
--operation mode is normal

JC8_out[4]_lut_out = JC8_out[3] $ JC8_out[1] $ JC8_out[4] $ P1_q_b[4];
JC8_out[4] = DFFEAS(JC8_out[4]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--W1L12 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|always2~784
--operation mode is normal

W1L12 = JC8_out[2] # JC8_out[1] # JC8_out[0] # JC8_out[4];


--JC9_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit|out[3]
--operation mode is normal

JC9_out[3]_lut_out = JC9_out[3] $ JC9_out[1] $ JC9_out[4] $ P1_q_b[3];