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RS编码的verilog源代码

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--L1_out is RSDecoder:inst1|Dec2Bit:Dec2Bit|out
--operation mode is normal

L1_out_lut_out = L1_cnt[2] & L1L3 # !L1_cnt[2] & (L1L5);
L1_out = DFFEAS(L1_out_lut_out, KC1_clk_out, reset, , L1_enable, , , , );


--L1_outstart is RSDecoder:inst1|Dec2Bit:Dec2Bit|outstart
--operation mode is normal

L1_outstart_lut_out = !L1_cnt[2] & !L1_cnt[0] & !L1_cnt[1];
L1_outstart = DFFEAS(L1_outstart_lut_out, KC1_clk_out, reset, , L1_enable, , , , );


--Y1_state1.st1_4 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_4
--operation mode is normal

Y1_state1.st1_4_lut_out = Y1_state1.st1_3 & Y1L39;
Y1_state1.st1_4 = DFFEAS(Y1_state1.st1_4_lut_out, M3_clk_out, reset, , , , , , );


--Y1_state1.st1_11 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_11
--operation mode is normal

Y1_state1.st1_11_lut_out = Y1L44 & !Y1L3 & (Y1_state1.st1_9 # Y1_state1.st1_8);
Y1_state1.st1_11 = DFFEAS(Y1_state1.st1_11_lut_out, M3_clk_out, reset, , , , , , );


--Y1_state1.st1_10 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_10
--operation mode is normal

Y1_state1.st1_10_lut_out = Y1L44 & Y1_state1.st1_7 & (!Y1L3);
Y1_state1.st1_10 = DFFEAS(Y1_state1.st1_10_lut_out, M3_clk_out, reset, , , , , , );


--Y1_decode_fail is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|decode_fail
--operation mode is normal

Y1_decode_fail = Y1_state1.st1_11 # Y1_state1.st1_10;


--D1_out is nrz:inst2|out
--operation mode is normal

D1_out_lut_out = D1_c5;
D1_out = DFFEAS(D1_out_lut_out, KC1_clk_out, reset, , , , , , );


--D1_datastart is nrz:inst2|datastart
--operation mode is normal

D1_datastart_lut_out = D1_datastart & (D1_cnt[1] $ D1_cnt[0] # !D1_cnt[2]) # !D1_datastart & D1_cnt[1] & D1_cnt[0] & !D1_cnt[2];
D1_datastart = DFFEAS(D1_datastart_lut_out, KC1_clk_out, reset, , , , , , );


--F1_errorout is error:inst6|errorout
--operation mode is normal

F1_errorout_lut_out = F1L4 & (F1_cnt[6] & !F1L1 & !F1_cnt[1] # !F1_cnt[6] & (F1L1 $ F1_cnt[1]));
F1_errorout = DFFEAS(F1_errorout_lut_out, MC1__clk0, VCC, , , , , , );


--inst17 is inst17
--operation mode is normal

inst17_lut_out = F1_errorout $ L2_out;
inst17 = DFFEAS(inst17_lut_out, MC1__clk0, VCC, , , , , , );


--L2_out is RSEncoder:inst|Dec2Bit:E|out
--operation mode is normal

L2_out_lut_out = L2_cnt[2] & (L2L4 # L2L5) # !L2_cnt[2] & L2L3;
L2_out = DFFEAS(L2_out_lut_out, MC1__clk0, reset, , L2_enable, , , , );


--L1_buff[0] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0]
--operation mode is normal

L1_buff[0]_lut_out = L1_cnt[0] & (L1L1 & P2_q_b[0] # !L1L1 & (L1_buff[0])) # !L1_cnt[0] & (L1_buff[0]);
L1_buff[0] = DFFEAS(L1_buff[0]_lut_out, KC1_clk_out, VCC, , L1L12, , , , );


--L1_buff[1] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[1]
--operation mode is normal

L1_buff[1]_lut_out = L1_cnt[0] & (L1L1 & P2_q_b[1] # !L1L1 & (L1_buff[1])) # !L1_cnt[0] & (L1_buff[1]);
L1_buff[1] = DFFEAS(L1_buff[1]_lut_out, KC1_clk_out, VCC, , L1L12, , , , );


--L1_cnt[0] is RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[0]
--operation mode is normal

L1_cnt[0]_lut_out = L1_cnt[2] # !L1_cnt[0];
L1_cnt[0] = DFFEAS(L1_cnt[0]_lut_out, KC1_clk_out, reset, , L1_enable, , , , );


--L1L2 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~317
--operation mode is normal

L1L2 = L1_cnt[0] & L1_buff[0] # !L1_cnt[0] & (L1_buff[1]);


--L1_cnt[1] is RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[1]
--operation mode is normal

L1_cnt[1]_lut_out = !L1_cnt[2] & (L1_cnt[0] $ L1_cnt[1]);
L1_cnt[1] = DFFEAS(L1_cnt[1]_lut_out, KC1_clk_out, reset, , L1_enable, , , , );


--L1L3 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~318
--operation mode is normal

L1L3 = L1_cnt[1] & L1_out # !L1_cnt[1] & (L1L2);


--P2_q_b[3] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P2_q_b[3]_PORT_A_data_in = X13_out[1];
P2_q_b[3]_PORT_A_data_in_reg = DFFE(P2_q_b[3]_PORT_A_data_in, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[3]_PORT_A_address_reg = DFFE(P2_q_b[3]_PORT_A_address, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[3]_PORT_B_address_reg = DFFE(P2_q_b[3]_PORT_B_address, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_PORT_A_write_enable = S1_wren;
P2_q_b[3]_PORT_A_write_enable_reg = DFFE(P2_q_b[3]_PORT_A_write_enable, P2_q_b[3]_clock_0, , , P2_q_b[3]_clock_enable_0);
P2_q_b[3]_PORT_B_read_enable = VCC;
P2_q_b[3]_PORT_B_read_enable_reg = DFFE(P2_q_b[3]_PORT_B_read_enable, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3]_clock_0 = M3_clk_out;
P2_q_b[3]_clock_1 = M1_clk_out;
P2_q_b[3]_clock_enable_0 = S1_wrclocken;
P2_q_b[3]_clock_enable_1 = S1_rdclocken;
P2_q_b[3]_PORT_B_data_out = MEMORY(P2_q_b[3]_PORT_A_data_in_reg, , P2_q_b[3]_PORT_A_address_reg, P2_q_b[3]_PORT_B_address_reg, P2_q_b[3]_PORT_A_write_enable_reg, P2_q_b[3]_PORT_B_read_enable_reg, , , P2_q_b[3]_clock_0, P2_q_b[3]_clock_1, P2_q_b[3]_clock_enable_0, P2_q_b[3]_clock_enable_1, , );
P2_q_b[3]_PORT_B_data_out_reg = DFFE(P2_q_b[3]_PORT_B_data_out, P2_q_b[3]_clock_1, , , P2_q_b[3]_clock_enable_1);
P2_q_b[3] = P2_q_b[3]_PORT_B_data_out_reg[0];


--L1_buff[3] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[3]
--operation mode is normal

L1_buff[3]_lut_out = L1L13;
L1_buff[3] = DFFEAS(L1_buff[3]_lut_out, KC1_clk_out, VCC, , L1L12, , , , );


--L1_cnt[2] is RSDecoder:inst1|Dec2Bit:Dec2Bit|cnt[2]
--operation mode is normal

L1_cnt[2]_lut_out = L1_cnt[2] & (!L1_cnt[0] & !L1_cnt[1]) # !L1_cnt[2] & (L1_cnt[0] & L1_cnt[1]);
L1_cnt[2] = DFFEAS(L1_cnt[2]_lut_out, KC1_clk_out, reset, , L1_enable, , , , );


--L1L1 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Equal~149
--operation mode is normal

L1L1 = !L1_cnt[2] & !L1_cnt[1];


--L1L13 is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1117
--operation mode is normal

L1L13 = L1_cnt[0] & (L1L1 & P2_q_b[3] # !L1L1 & (L1_buff[3])) # !L1_cnt[0] & (L1_buff[3]);


--P2_q_b[4] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P2_q_b[4]_PORT_A_data_in = X13_out[0];
P2_q_b[4]_PORT_A_data_in_reg = DFFE(P2_q_b[4]_PORT_A_data_in, P2_q_b[4]_clock_0, , , P2_q_b[4]_clock_enable_0);
P2_q_b[4]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[4]_PORT_A_address_reg = DFFE(P2_q_b[4]_PORT_A_address, P2_q_b[4]_clock_0, , , P2_q_b[4]_clock_enable_0);
P2_q_b[4]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[4]_PORT_B_address_reg = DFFE(P2_q_b[4]_PORT_B_address, P2_q_b[4]_clock_1, , , P2_q_b[4]_clock_enable_1);
P2_q_b[4]_PORT_A_write_enable = S1_wren;
P2_q_b[4]_PORT_A_write_enable_reg = DFFE(P2_q_b[4]_PORT_A_write_enable, P2_q_b[4]_clock_0, , , P2_q_b[4]_clock_enable_0);
P2_q_b[4]_PORT_B_read_enable = VCC;
P2_q_b[4]_PORT_B_read_enable_reg = DFFE(P2_q_b[4]_PORT_B_read_enable, P2_q_b[4]_clock_1, , , P2_q_b[4]_clock_enable_1);
P2_q_b[4]_clock_0 = M3_clk_out;
P2_q_b[4]_clock_1 = M1_clk_out;
P2_q_b[4]_clock_enable_0 = S1_wrclocken;
P2_q_b[4]_clock_enable_1 = S1_rdclocken;
P2_q_b[4]_PORT_B_data_out = MEMORY(P2_q_b[4]_PORT_A_data_in_reg, , P2_q_b[4]_PORT_A_address_reg, P2_q_b[4]_PORT_B_address_reg, P2_q_b[4]_PORT_A_write_enable_reg, P2_q_b[4]_PORT_B_read_enable_reg, , , P2_q_b[4]_clock_0, P2_q_b[4]_clock_1, P2_q_b[4]_clock_enable_0, P2_q_b[4]_clock_enable_1, , );
P2_q_b[4]_PORT_B_data_out_reg = DFFE(P2_q_b[4]_PORT_B_data_out, P2_q_b[4]_clock_1, , , P2_q_b[4]_clock_enable_1);
P2_q_b[4] = P2_q_b[4]_PORT_B_data_out_reg[0];


--L1_buff[4] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]
--operation mode is normal

L1_buff[4]_lut_out = L1L14;
L1_buff[4] = DFFEAS(L1_buff[4]_lut_out, KC1_clk_out, VCC, , L1L12, , , , );


--L1L14 is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1118
--operation mode is normal

L1L14 = L1_cnt[0] & (L1L1 & P2_q_b[4] # !L1L1 & (L1_buff[4])) # !L1_cnt[0] & (L1_buff[4]);


--L1L4 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~319
--operation mode is normal

L1L4 = L1_cnt[1] & (L1_cnt[0]) # !L1_cnt[1] & (L1_cnt[0] & L1L14 # !L1_cnt[0] & (L1_out));


--P2_q_b[2] is RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 5, Port B Logical Depth: 32, Port B Logical Width: 5
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
P2_q_b[2]_PORT_A_data_in = X13_out[2];
P2_q_b[2]_PORT_A_data_in_reg = DFFE(P2_q_b[2]_PORT_A_data_in, P2_q_b[2]_clock_0, , , P2_q_b[2]_clock_enable_0);
P2_q_b[2]_PORT_A_address = BUS(S1_wraddress[0], S1_wraddress[1], S1_wraddress[2], S1_wraddress[3], S1_wraddress[4]);
P2_q_b[2]_PORT_A_address_reg = DFFE(P2_q_b[2]_PORT_A_address, P2_q_b[2]_clock_0, , , P2_q_b[2]_clock_enable_0);
P2_q_b[2]_PORT_B_address = BUS(S1_rdaddress[0], S1_rdaddress[1], S1_rdaddress[2], S1_rdaddress[3], S1_rdaddress[4]);
P2_q_b[2]_PORT_B_address_reg = DFFE(P2_q_b[2]_PORT_B_address, P2_q_b[2]_clock_1, , , P2_q_b[2]_clock_enable_1);
P2_q_b[2]_PORT_A_write_enable = S1_wren;
P2_q_b[2]_PORT_A_write_enable_reg = DFFE(P2_q_b[2]_PORT_A_write_enable, P2_q_b[2]_clock_0, , , P2_q_b[2]_clock_enable_0);
P2_q_b[2]_PORT_B_read_enable = VCC;
P2_q_b[2]_PORT_B_read_enable_reg = DFFE(P2_q_b[2]_PORT_B_read_enable, P2_q_b[2]_clock_1, , , P2_q_b[2]_clock_enable_1);
P2_q_b[2]_clock_0 = M3_clk_out;
P2_q_b[2]_clock_1 = M1_clk_out;
P2_q_b[2]_clock_enable_0 = S1_wrclocken;
P2_q_b[2]_clock_enable_1 = S1_rdclocken;
P2_q_b[2]_PORT_B_data_out = MEMORY(P2_q_b[2]_PORT_A_data_in_reg, , P2_q_b[2]_PORT_A_address_reg, P2_q_b[2]_PORT_B_address_reg, P2_q_b[2]_PORT_A_write_enable_reg, P2_q_b[2]_PORT_B_read_enable_reg, , , P2_q_b[2]_clock_0, P2_q_b[2]_clock_1, P2_q_b[2]_clock_enable_0, P2_q_b[2]_clock_enable_1, , );
P2_q_b[2]_PORT_B_data_out_reg = DFFE(P2_q_b[2]_PORT_B_data_out, P2_q_b[2]_clock_1, , , P2_q_b[2]_clock_enable_1);
P2_q_b[2] = P2_q_b[2]_PORT_B_data_out_reg[0];


--L1_buff[2] is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[2]
--operation mode is normal

L1_buff[2]_lut_out = L1L15;
L1_buff[2] = DFFEAS(L1_buff[2]_lut_out, KC1_clk_out, VCC, , L1L12, , , , );


--L1L15 is RSDecoder:inst1|Dec2Bit:Dec2Bit|buff~1119
--operation mode is normal

L1L15 = L1_cnt[0] & (L1L1 & P2_q_b[2] # !L1L1 & (L1_buff[2])) # !L1_cnt[0] & (L1_buff[2]);


--L1L5 is RSDecoder:inst1|Dec2Bit:Dec2Bit|Select~320
--operation mode is normal

L1L5 = L1_cnt[1] & (L1L4 & (L1L15) # !L1L4 & L1L13) # !L1_cnt[1] & (L1L4);


--KC1_clk_temp1 is Clock:inst3|divide3:divideb|clk_temp1
--operation mode is normal

KC1_clk_temp1_lut_out = KC1_clk_temp1 $ (!KC1_counter[2] & (KC1_counter[1] $ KC1_counter[0]));
KC1_clk_temp1 = DFFEAS(KC1_clk_temp1_lut_out, clk, VCC, , , , , , );


--KC1_clk_temp2 is Clock:inst3|divide3:divideb|clk_temp2
--operation mode is normal

KC1_clk_temp2_lut_out = KC1_clk_temp1;
KC1_clk_temp2 = DFFEAS(KC1_clk_temp2_lut_out, !clk, VCC, , , , , , );


--KC1_clk_out is Clock:inst3|divide3:divideb|clk_out
--operation mode is normal

KC1_clk_out = KC1_clk_temp1 # KC1_clk_temp2;


--L1_enable is RSDecoder:inst1|Dec2Bit:Dec2Bit|enable
--operation mode is normal

L1_enable_lut_out = VCC;
L1_enable = DFFEAS(L1_enable_lut_out, !S1_wordstart, reset, , , , , , );


--Y1_state1.st1_3 is RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_3
--operation mode is normal

Y1_state1.st1_3_lut_out = Y1_state1.st1_11 & (Y1_state2.st2_10 # Y1_state2.st2_2) # !Y1_state1.st1_11 & Y1_state1.st1_2 & (Y1_state2.st2_10 # Y1_state2.st2_2);
Y1_state1.st1_3 = DFFEAS(Y1_state1.st1_3_lut_out, M3_clk_out, reset, , , , , , );


--W1_state.st2 is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|state.st2
--operation mode is normal

W1_state.st2_lut_out = Y1_state1.st1_3 & W1_state.st1;
W1_state.st2 = DFFEAS(W1_state.st2_lut_out, !M3_clk_out, reset, , , , , , );


--JC1_out[3] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[3]
--operation mode is normal

JC1_out[3]_lut_out = JC1_out[0] $ JC1_out[4] $ (P1_q_b[3]);
JC1_out[3] = DFFEAS(JC1_out[3]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC1_out[2] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[2]
--operation mode is normal

JC1_out[2]_lut_out = X1_out[2];
JC1_out[2] = DFFEAS(JC1_out[2]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC1_out[1] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[1]
--operation mode is normal

JC1_out[1]_lut_out = JC1_out[3] $ JC1_out[2] $ JC1_out[0] $ P1_q_b[1];
JC1_out[1] = DFFEAS(JC1_out[1]_lut_out, M3_clk_out, VCC, , !Y1_state2.st2_3, , , Y1L42, );


--JC1_out[0] is RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit|out[0]
--operation mode is normal

JC1_out[0]_lut_out = JC1_out[2] $ JC1_out[1] $ (P1_q_b[0]);