📄 cnt0.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt0 is
port(clk: in std_logic;
nao: in std_logic;
adj: in std_logic;
adjust:in std_logic_vector(4 downto 0);
ringnao,ringzheng:out std_logic;
qsl:out std_logic_vector(3 downto 0);
qsh:out std_logic_vector(3 downto 0);
qml:out std_logic_vector(3 downto 0);
qmh:out std_logic_vector(3 downto 0);
qhl:out std_logic_vector(3 downto 0);
qhh:out std_logic_vector(3 downto 0));
end cnt0;
architecture a of cnt0 is
signal inter_clk:std_logic;
signal tqsl,tqsh,tqml,tqmh,tqhh,tqhl,naotqsl,naotqsh,naotqml,naotqmh,naotqhh,
naotqhl:integer range 0 to 10;
signal tqh,naotqh:integer range 0 to 25;
begin
inter_clk<= clk or adj;
tqhl<= tqh when tqh>=0 and tqh<10 else
tqh-10 when tqh>=10 and tqh<20 else
tqh-20 when tqh>=20 and tqh<24 else
0;
tqhh<= 0 when tqh>=0 and tqh<10 else
1 when tqh>=10 and tqh<20 else
2 when tqh>=20 and tqh<24 else
0;
naotqhl<= tqh when naotqh>=0 and naotqh<10 else
naotqh-10 when naotqh>=10 and naotqh<20 else
naotqh-20 when naotqh>=20 and naotqh<24 else
0;
naotqhh<= 0 when naotqh>=0 and naotqh<10 else
1 when naotqh>=10 and naotqh<20 else
2 when naotqh>=20 and naotqh<24 else
0;
process(inter_clk)
begin
if(inter_clk'event and inter_clk='1' ) then
if (nao='1') then
--sec
if (adj='0' and tqsl=9)or(adjust="00001"and tqsl=9)then tqsl<=0;
elsif (adj='0' and tqsl/=9)or (adjust="00001" and tqsl/=9) then tqsl<=tqsl+1;
else tqsl<=tqsl;
end if;
if(adj='0' and tqsh=5 and tqsl=9)or(adjust(1)='1' and tqsh=5) then
tqsh<=0;
elsif(adj='0' and tqsh/=5 and tqsl=9)or(adjust(1)='1' and tqsh/=5) then
tqsh<=tqsh+1;
else tqsh<=tqsh;
end if;
--min;
if (adj='0' and tqml=9 and tqsh=5 and tqsl=9)or (adjust(2)='1' and tqml=9)then
tqml<=0;
elsif (adj='0' and tqml/=9 and tqsh=5 and tqsl=9)or(adjust(2)='1' and tqml/=9)then
tqml<=tqml+1;
else tqml<=tqml;
end if;
if(adj='0' and tqmh=5 and tqml=9 and tqsh=5 and tqsl=9)or(adjust(3)='1' and tqmh=5)then
tqmh<=0;
elsif (adj='0' and tqmh/=5 and tqml=9 and tqsh=5 and tqsl=9)or (adjust(3)='1'and tqmh/=5)then
tqmh<=tqmh+1;
else tqmh<=tqmh;
end if;
--hour
if(adj='0' and tqh=23 and tqmh=5 and tqml=9 and tqsh=5 and tqsl=9)or(adjust(4)='1' and tqh=23)
then tqh<=0;
elsif(adj='0' and tqh/=23 and tqmh=5 and tqml=9 and tqsh=5 and tqsl=9)or(adjust(4)='1' and tqh/=23)
then tqh<=tqh+1;
else tqh<=tqh;
qsl<=conv_std_logic_vector(tqsl,4);
qsh<=conv_std_logic_vector(tqsh,4);
qml<=conv_std_logic_vector(tqml,4);
qmh<=conv_std_logic_vector(tqmh,4);
qhl<=conv_std_logic_vector(tqhl,4);
qhh<=conv_std_logic_vector(tqhh,4);
end if;
else
--sec
if (adjust="00001"and naotqsl=9)then naotqsl<=0;
elsif(adjust="00001" and naotqsl/=9) then naotqsl<=naotqsl+1;
else naotqsl<=naotqsl;
end if;
if (adjust(1)='1' and naotqsh=5) then naotqsh<=0;
elsif (adjust(1)='1' and naotqsh/=5) then
naotqsh<=naotqsh+1;
else naotqsh<=naotqsh;
end if;
--min;
if (adjust(2)='1' and naotqml=9)then
naotqml<=0;
elsif (adjust(2)='1' and naotqml/=9)then
naotqml<=naotqml+1;
else naotqml<=naotqml;
end if;
if(adjust(3)='1' and naotqmh=5)then
naotqmh<=0;
elsif (adjust(3)='1'and naotqmh/=5)then
naotqmh<=naotqmh+1;
else naotqmh<=naotqmh;
end if;
--hour
if(adjust(4)='1' and naotqh=23)
then naotqh<=0;
elsif(adjust(4)='1' and naotqh/=23)
then naotqh<=tqh+1;
else naotqh<=naotqh;
end if;
qsl<=conv_std_logic_vector(naotqsl,4);
qsh<=conv_std_logic_vector(naotqsh,4);
qml<=conv_std_logic_vector(naotqml,4);
qmh<=conv_std_logic_vector(naotqmh,4);
qhl<=conv_std_logic_vector(naotqhl,4);
qhh<=conv_std_logic_vector(naotqhh,4);
end if;
end if;
end process;
process(clk)
begin
if (tqsl=naotqsl and tqsh=naotqsh and tqml=naotqml and tqmh=naotqmh and tqh=naotqh) then
ringnao<='1';
end if;
if (tqmh=5 and tqml=9 and tqsh=5 and tqsl=9) then
ringzheng<='1';
end if;
end process;
end ;
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