test_ulaw2int.v

来自「这是一个量化编码当中关于A律和u律压缩和扩展的源程序」· Verilog 代码 · 共 29 行

// file:  test_ulaw2int.v

`timescale 10ns/1ns
`include   "ulaw2int.v"
module test_ulaw2int;
reg[7:0]        ulaw;       // Input
reg             clk;
wire[15:0]      law16_int;  // Output
integer         i;

ulaw2int        ulaw_law16(clk,ulaw,law16_int);

initial  #0   clk=1'b0;
always   #10  clk=~clk;

initial
begin
    for(i=0;i<256;i=i+1)
    #10   ulaw=i;
end

initial
begin
    $monitor($time,,," The u-law %h convert to law16 format is %h",ulaw,law16_int);
    #2570 $finish;
end

endmodule