sim_linear2ulaw.v

来自「这是一个量化编码当中关于A律和u律压缩和扩展的源程序」· Verilog 代码 · 共 42 行

`timescale 1ns/1ns
`include   "linear2ulaw.v"
module     sim_linear2ulaw;

//input        clk;
//output[15:0] linear;
//output[7:0]  ulaw;
//input       clk;
integer     linear;
reg[7:0]    ulaw;
//reg[15:0]  temp_linear;
//reg        clk;
integer    i;

/*
initial
begin
    temp_linear=linear;
end
*/

linear2ulaw linear2law(clk,ulaw);


//always #5  clk=~clk;



initial
begin
    for(i=0;i<"16h0FF";i=i+1)
    #5  linear=i;
end


initial
begin
    $monitor($time,,,"The linear number %d convert to ulaw is %d",linear,ulaw);
    #160 $finish;
end
endmodule