test_int2alaw.v

来自「这是一个量化编码当中关于A律和u律压缩和扩展的源程序」· Verilog 代码 · 共 29 行

// file: test_int2alaw.v

`timescale    10ns/1ns
`include      "int2alaw.v"
module test_int2alaw;
reg[15:0]   law16_int;    //Input
reg         clk;
wire[7:0]   alaw;         //Output
integer     i;

int2alaw    law16_alaw(clk,law16_int,alaw);

initial     #0  clk=1'b0;
always      #10 clk=~clk;

initial
begin
    for(i=0;i<65535;i=i+8)
    #10     law16_int=i;
end

initial
begin
    $monitor($time,,," The  number %b convert to a-law is %b",law16_int,alaw);
    #81930 $finish;
end

endmodule