📄 test_ulaw2int.v
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// file: test_ulaw2int.v`timescale 10ns/1ns`include "ulaw2int.v"module test_ulaw2int;reg[7:0] ulaw; // Inputreg clk;wire[15:0] law16_int; // Outputinteger i;ulaw2int ulaw_law16(clk,ulaw,law16_int);initial #0 clk=1'b0;always #10 clk=~clk;initialbegin for(i=0;i<256;i=i+1) #10 ulaw=i;endinitialbegin $monitor($time,,," The u-law %h convert to law16 format is %h",ulaw,law16_int); #2570 $finish;endendmodule
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