ulaw2int.v

来自「这是一个量化编码当中关于A律和u律压缩和扩展的源程序」· Verilog 代码 · 共 42 行

// input: 8-bit code of u-law compression
// output:The integer of law16 format
// file:  ulaw2int.v

module ulaw2int(clk,ulaw,law16_int);
output[15:0]   law16_int;
input[7:0]     ulaw;
input          clk;
reg[15:0]      law16_int;
reg[12:0]      int;
reg[2:0]       segment;
reg[3:0]       quant;
reg            sign;
always@(posedge clk)
begin
    sign=ulaw[7];
    quant=ulaw[3:0];
    segment=ulaw[6:4];
    case(segment)
        3'b000: int={8'b00000001,quant,1'b1};
        3'b001: int={7'b0000001,quant,2'b10};
        3'b010: int={6'b000001,quant,3'b100};
        3'b011: int={5'b00001,quant,4'b1000};
        3'b100: int={4'b0001,quant,5'b10000};
        3'b101: int={3'b001,quant,6'b100000};
        3'b110: int={2'b01,quant,7'b1000000};
        3'b111: int={1'b1,quant,8'b10000000};
    endcase
    begin
        if(sign==1'b1)
           int=33-int;
        else
           int=int-33;
    end
    law16_int={sign,int,2'b00};
end
endmodule