int2alaw.v

来自「这是一个量化编码当中关于A律和u律压缩和扩展的源程序」· Verilog 代码 · 共 64 行

// input: The integer of law16 format
// output:8-bit code of a-law compression
// file:  int2alaw.v

module int2alaw(clk,law16_int,alaw);
output[7:0]   alaw;
input[15:0]   law16_int;
input         clk;
reg[11:0]     int;
reg[7:0]      alaw;
reg[3:0]      quant;
reg[2:0]      segment;
reg           sign;
always@(posedge clk)
  begin
      sign=law16_int[15];
      int=law16_int[14:3];
      casez(int)
        12'b0000000?????:
          begin
             segment=3'b000;
             quant=int[4:1];
          end
        12'b0000001?????:
          begin
             segment=3'b001;
             quant=int[4:1];
          end
        12'b000001??????:
          begin
             segment=3'b010;
             quant=int[5:2];
          end
        12'b00001???????:
          begin
             segment=3'b011;
             quant=int[6:3];
          end
        12'b0001????????:
          begin
             segment=3'b100;
             quant=int[7:4];
          end
        12'b001?????????:
          begin
             segment=3'b101;
             quant=int[8:5];
          end
        12'b01??????????:
          begin
             segment=3'b110;
             quant=int[9:6];
          end
        12'b1???????????:
          begin
             segment=3'b111;
             quant=int[10:7];
          end
      endcase
      alaw={sign,segment,quant};
  end
endmodule