📄 test_int2alaw.v
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// file: test_int2alaw.v`timescale 10ns/1ns`include "int2alaw.v"module test_int2alaw;reg[15:0] law16_int; //Inputreg clk;wire[7:0] alaw; //Outputinteger i;int2alaw law16_alaw(clk,law16_int,alaw);initial #0 clk=1'b0;always #10 clk=~clk;initialbegin for(i=0;i<65535;i=i+8) #10 law16_int=i;endinitialbegin $monitor($time,,," The number %b convert to a-law is %b",law16_int,alaw); #81930 $finish;endendmodule
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