📄 sim_linear2ulaw.v
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`timescale 1ns/1ns`include "linear2ulaw.v"module sim_linear2ulaw;//input clk;//output[15:0] linear;//output[7:0] ulaw;//input clk;integer linear;reg[7:0] ulaw;//reg[15:0] temp_linear;//reg clk;integer i;/*initialbegin temp_linear=linear;end*/linear2ulaw linear2law(clk,ulaw);//always #5 clk=~clk;initialbegin for(i=0;i<"16h0FF";i=i+1) #5 linear=i;endinitialbegin $monitor($time,,,"The linear number %d convert to ulaw is %d",linear,ulaw); #160 $finish;endendmodule
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