zxfg.txt

四位全加器语言描述是以文本方式上传的

library ieee;
use ieee.std_logic_1164.all;
entity jiang is
    port(a,b,cin:in std_logic;
    sum,cout:out std_logic);
end;
architecture a of jiang is
signal sig:std_logic_vector(2 downto 0);
begin
sig<=a&b&cin;
process(sig)
begin
case sig is
    when "000"=>sum<='0';cout<='0';
    when "001"=>sum<='1';cout<='0';
    when "010"=>sum<='1';cout<='0';
    when "011"=>sum<='0';cout<='1';
    when "100"=>sum<='1';cout<='0';
    when "101"=>sum<='0';cout<='1';
    when "110"=>sum<='0';cout<='1';
    when "111"=>sum<='1';cout<='1';
    when others=>NULL;
end case;
end process;
end architecture a;