fifo89_map.map

在ISE环境下用VHDL写的8*9FIFO

Release 9.1.03i Map J.33
Xilinx Map Application Log File for Design 'fifo89'

Design Information
------------------
Command Line   : G:\Xilinx91i\bin\nt\map.exe -ise
F:/vhdl/fifos/fifo_exp1/fifo_exp1.ise -intstyle ise -p xc2s15-cs144-6 -cm area
-pr b -k 4 -c 100 -tx off -o fifo89_map.ncd fifo89.ngd fifo89.pcf 
Target Device  : xc2s15
Target Package : cs144
Target Speed   : -6
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Sat Dec 08 16:33:25 2007

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:        69 out of    384   17%
  Number of 4 input LUTs:            52 out of    384   13%
Logic Distribution:
    Number of occupied Slices:                          61 out of    192   31%
    Number of Slices containing only related logic:     61 out of     61  100%
    Number of Slices containing unrelated logic:         0 out of     61    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        52 out of    384   13%
   Number of bonded IOBs:            25 out of     86   29%
      IOB Flip Flops:                               9
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,044
Additional JTAG gate count for IOBs:  1,248
Peak Memory Usage:  119 MB
Total REAL time to MAP completion:  1 secs 
Total CPU time to MAP completion:   1 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "fifo89_map.mrp" for details.