fifo89_timesim.vhd

在ISE环境下用VHDL写的8*9FIFO

      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_5_FFY_RST,
      O => fifo_6_4_16
    );
  fifo_6_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C8.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_5_FFY_RST
    );
  fifo_5_8 : X_FF
    generic map(
      LOC => "CLB_R4C5.S1",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_8_FFY_RST,
      O => fifo_5_8_17
    );
  fifo_5_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C5.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_8_FFY_RST
    );
  fifo_7_0 : X_FF
    generic map(
      LOC => "CLB_R3C7.S0",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_7_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_7_1_FFY_RST,
      O => fifo_7_0_19
    );
  fifo_7_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R3C7.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_7_1_FFY_RST
    );
  fifo_6_6 : X_FF
    generic map(
      LOC => "CLB_R7C8.S1",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_7_FFY_RST,
      O => fifo_6_6_21
    );
  fifo_6_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C8.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_7_FFY_RST
    );
  fifo_7_2 : X_FF
    generic map(
      LOC => "CLB_R5C5.S1",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_7_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_7_3_FFY_RST,
      O => fifo_7_2_23
    );
  fifo_7_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C5.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_7_3_FFY_RST
    );
  fifo_1_not00011 : X_LUT4
    generic map(
      INIT => X"0008",
      LOC => "CLB_R7C3.S0"
    )
    port map (
      ADR0 => wr_IBUF_0,
      ADR1 => wrptr(0),
      ADR2 => wrptr(2),
      ADR3 => wrptr(1),
      O => fifo_1_not0001
    );
  fifo_4_not00011 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "CLB_R7C3.S0"
    )
    port map (
      ADR0 => wr_IBUF_0,
      ADR1 => wrptr(0),
      ADR2 => wrptr(1),
      ADR3 => wrptr(2),
      O => fifo_4_not0001
    );
  fifo_1_not0001_XUSED : X_BUF
    generic map(
      LOC => "CLB_R7C3.S0"
    )
    port map (
      I => fifo_1_not0001,
      O => fifo_1_not0001_0
    );
  fifo_1_not0001_YUSED : X_BUF
    generic map(
      LOC => "CLB_R7C3.S0"
    )
    port map (
      I => fifo_4_not0001,
      O => fifo_4_not0001_0
    );
  fifo_6_8 : X_FF
    generic map(
      LOC => "CLB_R5C3.S1",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_8_FFY_RST,
      O => fifo_6_8_24
    );
  fifo_6_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C3.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_8_FFY_RST
    );
  fifo_7_4 : X_FF
    generic map(
      LOC => "CLB_R7C8.S0",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,
      CE => fifo_7_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_7_5_FFY_RST,
      O => fifo_7_4_26
    );
  fifo_7_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C8.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_7_5_FFY_RST
    );
  fifo_7_6 : X_FF
    generic map(
      LOC => "CLB_R8C7.S0",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_7_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_7_7_FFY_RST,
      O => fifo_7_6_28
    );
  fifo_7_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R8C7.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_7_7_FFY_RST
    );
  fifo_7_8 : X_FF
    generic map(
      LOC => "CLB_R4C6.S1",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_7_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_7_8_FFY_RST,
      O => fifo_7_8_29
    );
  fifo_7_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C6.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_7_8_FFY_RST
    );
  fifo_2_not00011 : X_LUT4
    generic map(
      INIT => X"0400",
      LOC => "CLB_R6C5.S1"
    )
    port map (
      ADR0 => wrptr(2),
      ADR1 => wr_IBUF_0,
      ADR2 => wrptr(0),
      ADR3 => wrptr(1),
      O => fifo_2_not0001
    );
  fifo_5_not00011 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "CLB_R6C5.S1"
    )
    port map (
      ADR0 => wr_IBUF_0,
      ADR1 => wrptr(2),
      ADR2 => wrptr(0),
      ADR3 => wrptr(1),
      O => fifo_5_not0001
    );
  fifo_2_not0001_XUSED : X_BUF
    generic map(
      LOC => "CLB_R6C5.S1"
    )
    port map (
      I => fifo_2_not0001,
      O => fifo_2_not0001_0
    );
  fifo_2_not0001_YUSED : X_BUF
    generic map(
      LOC => "CLB_R6C5.S1"
    )
    port map (
      I => fifo_5_not0001,
      O => fifo_5_not0001_0
    );
  fifo_7_not00011 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "CLB_R7C5.S0"
    )
    port map (
      ADR0 => wr_IBUF_0,
      ADR1 => wrptr(1),
      ADR2 => wrptr(0),
      ADR3 => wrptr(2),
      O => fifo_7_not0001
    );
  fifo_6_not00011 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "CLB_R7C5.S0"
    )
    port map (
      ADR0 => wr_IBUF_0,
      ADR1 => wrptr(1),
      ADR2 => wrptr(0),
      ADR3 => wrptr(2),
      O => fifo_6_not0001
    );
  fifo_7_not0001_XUSED : X_BUF
    generic map(
      LOC => "CLB_R7C5.S0"
    )
    port map (
      I => fifo_7_not0001,
      O => fifo_7_not0001_0
    );
  fifo_7_not0001_YUSED : X_BUF
    generic map(
      LOC => "CLB_R7C5.S0"
    )
    port map (
      I => fifo_6_not0001,
      O => fifo_6_not0001_0
    );
  Mcount_rdptr_xor_2_11 : X_LUT4
    generic map(
      INIT => X"0078",
      LOC => "CLB_R2C4.S1"
    )
    port map (
      ADR0 => rdptr(0),
      ADR1 => rdptr(1),
      ADR2 => rdptr(2),
      ADR3 => rdptrclr_IBUF_0,
      O => Mcount_rdptr6
    );
  rdptr_not00011 : X_LUT4
    generic map(
      INIT => X"FAFA",
      LOC => "CLB_R2C4.S1"
    )
    port map (
      ADR0 => rdinc_IBUF_0,
      ADR1 => VCC,
      ADR2 => rdptrclr_IBUF_0,
      ADR3 => VCC,
      O => rdptr_not0001_pack_1
    );
  rdptr_2_YUSED : X_BUF
    generic map(
      LOC => "CLB_R2C4.S1"
    )
    port map (
      I => rdptr_not0001_pack_1,
      O => rdptr_not0001
    );
  rdptr_2 : X_FF
    generic map(
      LOC => "CLB_R2C4.S1",
      INIT => '0'
    )
    port map (
      I => Mcount_rdptr6,
      CE => rdptr_not0001,
      CLK => clk_BUFGP,
      SET => GND,
      RST => rdptr_2_FFX_RST,
      O => rdptr(2)
    );
  rdptr_2_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R2C4.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => rdptr_2_FFX_RST
    );
  fifo_4_5 : X_FF
    generic map(
      LOC => "CLB_R6C9.S0",
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_5_FFX_RST,
      O => fifo_4_5_0
    );
  fifo_4_5_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C9.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_5_FFX_RST
    );
  fifo_5_3 : X_FF
    generic map(
      LOC => "CLB_R5C5.S0",
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_3_FFX_RST,
      O => fifo_5_3_2
    );
  fifo_5_3_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C5.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_3_FFX_RST
    );
  fifo_4_7 : X_FF
    generic map(
      LOC => "CLB_R8C6.S0",
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_7_FFX_RST,
      O => fifo_4_7_4
    );
  fifo_4_7_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R8C6.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_7_FFX_RST
    );
  fifo_6_1 : X_FF
    generic map(
      LOC => "CLB_R4C5.S0",
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_1_FFX_RST,
      O => fifo_6_1_6
    );
  fifo_6_1_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C5.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_1_FFX_RST
    );
  fifo_5_5 : X_FF
    generic map(
      LOC => "CLB_R5C7.S1",
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_5_FFX_RST,
      O => fifo_5_5_8
    );
  fifo_5_5_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C7.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_5_FFX_RST
    );
  fifo_6_3 : X_FF
    generic map(
      LOC => "CLB_R5C4.S0",
      INIT => '0'
    )
    port map (
      I => data_in_3_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_3_FFX_RST,
      O => fifo_6_3_11
    );
  fifo_6_3_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C4.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_3_FFX_RST
    );
  fifo_5_7 : X_FF
    generic map(
      LOC => "CLB_R5C7.S0",
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_7_FFX_RST,
      O => fifo_5_7_13
    );
  fifo_5_7_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C7.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_7_FFX_RST
    );
  fifo_6_5 : X_FF
    generic map(
      LOC => "CLB_R6C8.S1",
      INIT => '0'
    )
    port map (
      I => data_in_5_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_5_FFX_RST,
      O => fifo_6_5_15
    );
  fifo_6_5_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C8.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_5_FFX_RST
    );
  fifo_7_1 : X_FF
    generic map(
      LOC => "CLB_R3C7.S0",
      INIT => '0'
    )
    port map (
      I => data_in_1_IBUF_0,
      CE => fifo_7_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_7_1_FFX_RST,
      O => fifo_7_1_18
    );
  fifo_7_1_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R3C7.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_7_1_FFX_RST
    );
  fifo_6_7 : X_FF
    generic map(
      LOC => "CLB_R7C8.S1",
      INIT => '0'
    )
    port map (
      I => data_in_7_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_7_FFX_RST,
      O => fifo_6_7_20
    );
  fifo_6_7_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C8.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_7_FFX_RST
    );
  wrptr_1 : X_FF
    generic map(
      LOC => "CLB_R7C4.S1",
      INIT => '0'
    )
    port map (
      I => Mcount_wrptr3,
      CE => wrptr_not0001,
      CLK => clk_BUFGP,
      SET => GND,
      RST => wrptr_1_FFX_RST,
      O => wrptr(1)
    );
  wrptr_1_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C4.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => wrptr_1_FFX_RST
    );
  rdptr_1 : X_FF
    generic map(
      LOC => "CLB_R2C4.S0",
      INIT => '0'
    )
    port map (
      I => Mcount_rdptr3,
      CE => rdptr_not0001,
      CLK => clk_BUFGP,
      SET => GND,
      RST => rdptr_1_FFX_RST,
      O => rdptr(1)
    );
  rdptr_1_FFX_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R2C4.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => rdptr_1_FFX_RST