fifo89_timesim.vhd

在ISE环境下用VHDL写的8*9FIFO

      LOC => "PAD93"
    )
    port map (
      I => rdinc,
      O => rdinc_IBUF_83
    );
  wr_IMUX : X_BUF
    generic map(
      LOC => "PAD59"
    )
    port map (
      I => wr_IBUF_84,
      O => wr_IBUF_0
    );
  wr_IBUF : X_BUF
    generic map(
      LOC => "PAD59"
    )
    port map (
      I => wr,
      O => wr_IBUF_84
    );
  data_out_0_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD36"
    )
    port map (
      I => data_out_0_OUTMUX_85,
      CTL => data_out_0_TORGTS,
      O => data_out(0)
    );
  data_out_0_GTS_OR : X_INV
    generic map(
      LOC => "PAD36"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_0_TORGTS
    );
  data_out_0_OUTMUX : X_BUF
    generic map(
      LOC => "PAD36"
    )
    port map (
      I => dmuxout(0),
      O => data_out_0_OUTMUX_85
    );
  data_out_1_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD31"
    )
    port map (
      I => data_out_1_OUTMUX_86,
      CTL => data_out_1_TORGTS,
      O => data_out(1)
    );
  data_out_1_GTS_OR : X_INV
    generic map(
      LOC => "PAD31"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_1_TORGTS
    );
  data_out_1_OUTMUX : X_BUF
    generic map(
      LOC => "PAD31"
    )
    port map (
      I => dmuxout(1),
      O => data_out_1_OUTMUX_86
    );
  data_out_2_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD40"
    )
    port map (
      I => data_out_2_OUTMUX_87,
      CTL => data_out_2_TORGTS,
      O => data_out(2)
    );
  data_out_2_GTS_OR : X_INV
    generic map(
      LOC => "PAD40"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_2_TORGTS
    );
  data_out_2_OUTMUX : X_BUF
    generic map(
      LOC => "PAD40"
    )
    port map (
      I => dmuxout(2),
      O => data_out_2_OUTMUX_87
    );
  data_out_3_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD39"
    )
    port map (
      I => data_out_3_OUTMUX_88,
      CTL => data_out_3_TORGTS,
      O => data_out(3)
    );
  data_out_3_GTS_OR : X_INV
    generic map(
      LOC => "PAD39"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_3_TORGTS
    );
  data_out_3_OUTMUX : X_BUF
    generic map(
      LOC => "PAD39"
    )
    port map (
      I => dmuxout(3),
      O => data_out_3_OUTMUX_88
    );
  data_out_4_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD42"
    )
    port map (
      I => data_out_4_OUTMUX_89,
      CTL => data_out_4_TORGTS,
      O => data_out(4)
    );
  data_out_4_GTS_OR : X_INV
    generic map(
      LOC => "PAD42"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_4_TORGTS
    );
  data_out_4_OUTMUX : X_BUF
    generic map(
      LOC => "PAD42"
    )
    port map (
      I => dmuxout(4),
      O => data_out_4_OUTMUX_89
    );
  data_in_0_IMUX : X_BUF
    generic map(
      LOC => "PAD68"
    )
    port map (
      I => data_in_0_IBUF_90,
      O => data_in_0_IBUF_0
    );
  data_in_0_IBUF : X_BUF
    generic map(
      LOC => "PAD68"
    )
    port map (
      I => data_in(0),
      O => data_in_0_IBUF_90
    );
  data_in_0_DELAY : X_BUF
    generic map(
      LOC => "PAD68"
    )
    port map (
      I => data_in_0_IBUF_90,
      O => data_in_0_IDELAY
    );
  data_out_5_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD38"
    )
    port map (
      I => data_out_5_OUTMUX_91,
      CTL => data_out_5_TORGTS,
      O => data_out(5)
    );
  data_out_5_GTS_OR : X_INV
    generic map(
      LOC => "PAD38"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_5_TORGTS
    );
  data_out_5_OUTMUX : X_BUF
    generic map(
      LOC => "PAD38"
    )
    port map (
      I => dmuxout(5),
      O => data_out_5_OUTMUX_91
    );
  data_in_1_IMUX : X_BUF
    generic map(
      LOC => "PAD63"
    )
    port map (
      I => data_in_1_IBUF_92,
      O => data_in_1_IBUF_0
    );
  data_in_1_IBUF : X_BUF
    generic map(
      LOC => "PAD63"
    )
    port map (
      I => data_in(1),
      O => data_in_1_IBUF_92
    );
  data_in_1_DELAY : X_BUF
    generic map(
      LOC => "PAD63"
    )
    port map (
      I => data_in_1_IBUF_92,
      O => data_in_1_IDELAY
    );
  data_out_6_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD48"
    )
    port map (
      I => data_out_6_OUTMUX_93,
      CTL => data_out_6_TORGTS,
      O => data_out(6)
    );
  data_out_6_GTS_OR : X_INV
    generic map(
      LOC => "PAD48"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_6_TORGTS
    );
  data_out_6_OUTMUX : X_BUF
    generic map(
      LOC => "PAD48"
    )
    port map (
      I => dmuxout(6),
      O => data_out_6_OUTMUX_93
    );
  data_in_2_IMUX : X_BUF
    generic map(
      LOC => "PAD67"
    )
    port map (
      I => data_in_2_IBUF_94,
      O => data_in_2_IBUF_0
    );
  data_in_2_IBUF : X_BUF
    generic map(
      LOC => "PAD67"
    )
    port map (
      I => data_in(2),
      O => data_in_2_IBUF_94
    );
  data_in_2_DELAY : X_BUF
    generic map(
      LOC => "PAD67"
    )
    port map (
      I => data_in_2_IBUF_94,
      O => data_in_2_IDELAY
    );
  data_out_7_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD45"
    )
    port map (
      I => data_out_7_OUTMUX_95,
      CTL => data_out_7_TORGTS,
      O => data_out(7)
    );
  data_out_7_GTS_OR : X_INV
    generic map(
      LOC => "PAD45"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_7_TORGTS
    );
  data_out_7_OUTMUX : X_BUF
    generic map(
      LOC => "PAD45"
    )
    port map (
      I => dmuxout(7),
      O => data_out_7_OUTMUX_95
    );
  data_in_3_IMUX : X_BUF
    generic map(
      LOC => "PAD70"
    )
    port map (
      I => data_in_3_IBUF_96,
      O => data_in_3_IBUF_0
    );
  data_in_3_IBUF : X_BUF
    generic map(
      LOC => "PAD70"
    )
    port map (
      I => data_in(3),
      O => data_in_3_IBUF_96
    );
  data_in_3_DELAY : X_BUF
    generic map(
      LOC => "PAD70"
    )
    port map (
      I => data_in_3_IBUF_96,
      O => data_in_3_IDELAY
    );
  data_out_8_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD34"
    )
    port map (
      I => data_out_8_OUTMUX_97,
      CTL => data_out_8_TORGTS,
      O => data_out(8)
    );
  data_out_8_GTS_OR : X_INV
    generic map(
      LOC => "PAD34"
    )
    port map (
      I => rd_IBUF_0,
      O => data_out_8_TORGTS
    );
  data_out_8_OUTMUX : X_BUF
    generic map(
      LOC => "PAD34"
    )
    port map (
      I => dmuxout(8),
      O => data_out_8_OUTMUX_97
    );
  data_in_4_IMUX : X_BUF
    generic map(
      LOC => "PAD66"
    )
    port map (
      I => data_in_4_IBUF_98,
      O => data_in_4_IBUF_0
    );
  data_in_4_IBUF : X_BUF
    generic map(
      LOC => "PAD66"
    )
    port map (
      I => data_in(4),
      O => data_in_4_IBUF_98
    );
  data_in_4_DELAY : X_BUF
    generic map(
      LOC => "PAD66"
    )
    port map (
      I => data_in_4_IBUF_98,
      O => data_in_4_IDELAY
    );
  data_in_5_IMUX : X_BUF
    generic map(
      LOC => "PAD65"
    )
    port map (
      I => data_in_5_IBUF_99,
      O => data_in_5_IBUF_0
    );
  data_in_5_IBUF : X_BUF
    generic map(
      LOC => "PAD65"
    )
    port map (
      I => data_in(5),
      O => data_in_5_IBUF_99
    );
  data_in_5_DELAY : X_BUF
    generic map(
      LOC => "PAD65"
    )
    port map (
      I => data_in_5_IBUF_99,
      O => data_in_5_IDELAY
    );
  fifo_4_4 : X_FF
    generic map(
      LOC => "CLB_R6C9.S0",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_5_FFY_RST,
      O => fifo_4_4_1
    );
  fifo_4_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C9.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_5_FFY_RST
    );
  fifo_5_2 : X_FF
    generic map(
      LOC => "CLB_R5C5.S0",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_3_FFY_RST,
      O => fifo_5_2_3
    );
  fifo_5_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C5.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_3_FFY_RST
    );
  fifo_4_6 : X_FF
    generic map(
      LOC => "CLB_R8C6.S0",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_7_FFY_RST,
      O => fifo_4_6_5
    );
  fifo_4_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R8C6.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_7_FFY_RST
    );
  fifo_6_0 : X_FF
    generic map(
      LOC => "CLB_R4C5.S0",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_1_FFY_RST,
      O => fifo_6_0_7
    );
  fifo_6_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C5.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_1_FFY_RST
    );
  fifo_5_4 : X_FF
    generic map(
      LOC => "CLB_R5C7.S1",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_5_FFY_RST,
      O => fifo_5_4_9
    );
  fifo_5_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C7.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_5_FFY_RST
    );
  fifo_4_8 : X_FF
    generic map(
      LOC => "CLB_R6C3.S0",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_8_FFY_RST,
      O => fifo_4_8_10
    );
  fifo_4_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C3.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_8_FFY_RST
    );
  fifo_0_not00011 : X_LUT4
    generic map(
      INIT => X"0002",
      LOC => "CLB_R7C4.S0"
    )
    port map (
      ADR0 => wr_IBUF_0,
      ADR1 => wrptr(1),
      ADR2 => wrptr(0),
      ADR3 => wrptr(2),
      O => fifo_0_not0001
    );
  fifo_3_not00011 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "CLB_R7C4.S0"
    )
    port map (
      ADR0 => wrptr(1),
      ADR1 => wrptr(0),
      ADR2 => wr_IBUF_0,
      ADR3 => wrptr(2),
      O => fifo_3_not0001
    );
  fifo_0_not0001_XUSED : X_BUF
    generic map(
      LOC => "CLB_R7C4.S0"
    )
    port map (
      I => fifo_0_not0001,
      O => fifo_0_not0001_0
    );
  fifo_0_not0001_YUSED : X_BUF
    generic map(
      LOC => "CLB_R7C4.S0"
    )
    port map (
      I => fifo_3_not0001,
      O => fifo_3_not0001_0
    );
  fifo_6_2 : X_FF
    generic map(
      LOC => "CLB_R5C4.S0",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_6_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_6_3_FFY_RST,
      O => fifo_6_2_12
    );
  fifo_6_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C4.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_6_3_FFY_RST
    );
  fifo_5_6 : X_FF
    generic map(
      LOC => "CLB_R5C7.S0",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_7_FFY_RST,
      O => fifo_5_6_14
    );
  fifo_5_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C7.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_7_FFY_RST
    );
  fifo_6_4 : X_FF
    generic map(
      LOC => "CLB_R6C8.S1",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,