fifo89_timesim.vhd

在ISE环境下用VHDL写的8*9FIFO

  data_in_7_IMUX : X_BUF
    generic map(
      LOC => "PAD58"
    )
    port map (
      I => data_in_7_IBUF_76,
      O => data_in_7_IBUF_0
    );
  data_in_7_IBUF : X_BUF
    generic map(
      LOC => "PAD58"
    )
    port map (
      I => data_in(7),
      O => data_in_7_IBUF_76
    );
  data_in_7_DELAY : X_BUF
    generic map(
      LOC => "PAD58"
    )
    port map (
      I => data_in_7_IBUF_76,
      O => data_in_7_IDELAY
    );
  data_in_8_IMUX : X_BUF
    generic map(
      LOC => "PAD88"
    )
    port map (
      I => data_in_8_IBUF_77,
      O => data_in_8_IBUF_0
    );
  data_in_8_IBUF : X_BUF
    generic map(
      LOC => "PAD88"
    )
    port map (
      I => data_in(8),
      O => data_in_8_IBUF_77
    );
  data_in_8_DELAY : X_BUF
    generic map(
      LOC => "PAD88"
    )
    port map (
      I => data_in_8_IBUF_77,
      O => data_in_8_IDELAY
    );
  rdptrclr_IMUX : X_BUF
    generic map(
      LOC => "PAD91"
    )
    port map (
      I => rdptrclr_IBUF_78,
      O => rdptrclr_IBUF_0
    );
  rdptrclr_IBUF : X_BUF
    generic map(
      LOC => "PAD91"
    )
    port map (
      I => rdptrclr,
      O => rdptrclr_IBUF_78
    );
  rst_IMUX : X_BUF
    generic map(
      LOC => "PAD78"
    )
    port map (
      I => rst_IBUF_79,
      O => rst_IBUF_0
    );
  rst_IBUF : X_BUF
    generic map(
      LOC => "PAD78"
    )
    port map (
      I => rst,
      O => rst_IBUF_79
    );
  Mmux_dmuxout_4_f5_0 : X_MUX2
    generic map(
      LOC => "CLB_R3C5.S0"
    )
    port map (
      IA => N9,
      IB => N8,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f51
    );
  Mmux_dmuxout_53 : X_LUT4
    generic map(
      INIT => X"F3C0",
      LOC => "CLB_R3C5.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_3_1_40,
      ADR3 => fifo_2_1_39,
      O => N8
    );
  Mmux_dmuxout_61 : X_LUT4
    generic map(
      INIT => X"FA50",
      LOC => "CLB_R3C5.S0"
    )
    port map (
      ADR0 => rdptr(0),
      ADR1 => VCC,
      ADR2 => fifo_0_1_31,
      ADR3 => fifo_1_1_41,
      O => N9
    );
  Mmux_dmuxout_4_f51_F5USED : X_BUF
    generic map(
      LOC => "CLB_R3C5.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f51,
      O => Mmux_dmuxout_4_f51_0
    );
  Mmux_dmuxout_4_f5_1 : X_MUX2
    generic map(
      LOC => "CLB_R6C4.S0"
    )
    port map (
      IA => N13,
      IB => N12,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f52
    );
  Mmux_dmuxout_55 : X_LUT4
    generic map(
      INIT => X"F3C0",
      LOC => "CLB_R6C4.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_3_2_43,
      ADR3 => fifo_2_2_42,
      O => N12
    );
  Mmux_dmuxout_62 : X_LUT4
    generic map(
      INIT => X"E2E2",
      LOC => "CLB_R6C4.S0"
    )
    port map (
      ADR0 => fifo_0_2_32,
      ADR1 => rdptr(0),
      ADR2 => fifo_1_2_44,
      ADR3 => VCC,
      O => N13
    );
  Mmux_dmuxout_4_f52_F5USED : X_BUF
    generic map(
      LOC => "CLB_R6C4.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f52,
      O => Mmux_dmuxout_4_f52_0
    );
  Mmux_dmuxout_4_f5_2 : X_MUX2
    generic map(
      LOC => "CLB_R5C6.S0"
    )
    port map (
      IA => N17,
      IB => N16,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f53
    );
  Mmux_dmuxout_57 : X_LUT4
    generic map(
      INIT => X"BB88",
      LOC => "CLB_R5C6.S0"
    )
    port map (
      ADR0 => fifo_3_3_46,
      ADR1 => rdptr(0),
      ADR2 => VCC,
      ADR3 => fifo_2_3_45,
      O => N16
    );
  Mmux_dmuxout_63 : X_LUT4
    generic map(
      INIT => X"BB88",
      LOC => "CLB_R5C6.S0"
    )
    port map (
      ADR0 => fifo_1_3_47,
      ADR1 => rdptr(0),
      ADR2 => VCC,
      ADR3 => fifo_0_3_33,
      O => N17
    );
  Mmux_dmuxout_4_f53_F5USED : X_BUF
    generic map(
      LOC => "CLB_R5C6.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f53,
      O => Mmux_dmuxout_4_f53_0
    );
  Mmux_dmuxout_4_f5_3 : X_MUX2
    generic map(
      LOC => "CLB_R6C7.S0"
    )
    port map (
      IA => N211,
      IB => N20,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f54
    );
  Mmux_dmuxout_59 : X_LUT4
    generic map(
      INIT => X"B8B8",
      LOC => "CLB_R6C7.S0"
    )
    port map (
      ADR0 => fifo_3_4_49,
      ADR1 => rdptr(0),
      ADR2 => fifo_2_4_48,
      ADR3 => VCC,
      O => N20
    );
  Mmux_dmuxout_64 : X_LUT4
    generic map(
      INIT => X"FC30",
      LOC => "CLB_R6C7.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_0_4_34,
      ADR3 => fifo_1_4_50,
      O => N211
    );
  Mmux_dmuxout_4_f54_F5USED : X_BUF
    generic map(
      LOC => "CLB_R6C7.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f54,
      O => Mmux_dmuxout_4_f54_0
    );
  Mmux_dmuxout_4_f5_4 : X_MUX2
    generic map(
      LOC => "CLB_R5C8.S0"
    )
    port map (
      IA => N25,
      IB => N24,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f55
    );
  Mmux_dmuxout_511 : X_LUT4
    generic map(
      INIT => X"CCF0",
      LOC => "CLB_R5C8.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_3_5_52,
      ADR2 => fifo_2_5_51,
      ADR3 => rdptr(0),
      O => N24
    );
  Mmux_dmuxout_65 : X_LUT4
    generic map(
      INIT => X"F5A0",
      LOC => "CLB_R5C8.S0"
    )
    port map (
      ADR0 => rdptr(0),
      ADR1 => VCC,
      ADR2 => fifo_1_5_53,
      ADR3 => fifo_0_5_35,
      O => N25
    );
  Mmux_dmuxout_4_f55_F5USED : X_BUF
    generic map(
      LOC => "CLB_R5C8.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f55,
      O => Mmux_dmuxout_4_f55_0
    );
  Mmux_dmuxout_4_f5_5 : X_MUX2
    generic map(
      LOC => "CLB_R8C8.S0"
    )
    port map (
      IA => N29,
      IB => N28,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f56
    );
  Mmux_dmuxout_513 : X_LUT4
    generic map(
      INIT => X"AFA0",
      LOC => "CLB_R8C8.S0"
    )
    port map (
      ADR0 => fifo_3_6_55,
      ADR1 => VCC,
      ADR2 => rdptr(0),
      ADR3 => fifo_2_6_54,
      O => N28
    );
  Mmux_dmuxout_66 : X_LUT4
    generic map(
      INIT => X"E2E2",
      LOC => "CLB_R8C8.S0"
    )
    port map (
      ADR0 => fifo_0_6_36,
      ADR1 => rdptr(0),
      ADR2 => fifo_1_6_56,
      ADR3 => VCC,
      O => N29
    );
  Mmux_dmuxout_4_f56_F5USED : X_BUF
    generic map(
      LOC => "CLB_R8C8.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f56,
      O => Mmux_dmuxout_4_f56_0
    );
  Mmux_dmuxout_4_f5_6 : X_MUX2
    generic map(
      LOC => "CLB_R7C7.S0"
    )
    port map (
      IA => N33,
      IB => N32,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f57
    );
  Mmux_dmuxout_515 : X_LUT4
    generic map(
      INIT => X"FC0C",
      LOC => "CLB_R7C7.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_2_7_57,
      ADR2 => rdptr(0),
      ADR3 => fifo_3_7_58,
      O => N32
    );
  Mmux_dmuxout_67 : X_LUT4
    generic map(
      INIT => X"FC30",
      LOC => "CLB_R7C7.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_0_7_37,
      ADR3 => fifo_1_7_59,
      O => N33
    );
  Mmux_dmuxout_4_f57_F5USED : X_BUF
    generic map(
      LOC => "CLB_R7C7.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f57,
      O => Mmux_dmuxout_4_f57_0
    );
  Mmux_dmuxout_4_f5_7 : X_MUX2
    generic map(
      LOC => "CLB_R4C3.S0"
    )
    port map (
      IA => N37,
      IB => N36,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f58
    );
  Mmux_dmuxout_517 : X_LUT4
    generic map(
      INIT => X"FA50",
      LOC => "CLB_R4C3.S0"
    )
    port map (
      ADR0 => rdptr(0),
      ADR1 => VCC,
      ADR2 => fifo_2_8_60,
      ADR3 => fifo_3_8_61,
      O => N36
    );
  Mmux_dmuxout_68 : X_LUT4
    generic map(
      INIT => X"F0AA",
      LOC => "CLB_R4C3.S0"
    )
    port map (
      ADR0 => fifo_0_8_38,
      ADR1 => VCC,
      ADR2 => fifo_1_8_62,
      ADR3 => rdptr(0),
      O => N37
    );
  Mmux_dmuxout_4_f58_F5USED : X_BUF
    generic map(
      LOC => "CLB_R4C3.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f58,
      O => Mmux_dmuxout_4_f58_0
    );
  Mmux_dmuxout_3_f5_0 : X_MUX2
    generic map(
      LOC => "CLB_R3C5.S1"
    )
    port map (
      IA => N7,
      IB => N6,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f51
    );
  Mmux_dmuxout_41 : X_LUT4
    generic map(
      INIT => X"F0AA",
      LOC => "CLB_R3C5.S1"
    )
    port map (
      ADR0 => fifo_6_1_6,
      ADR1 => VCC,
      ADR2 => fifo_7_1_18,
      ADR3 => rdptr(0),
      O => N6
    );
  Mmux_dmuxout_52 : X_LUT4
    generic map(
      INIT => X"FC30",
      LOC => "CLB_R3C5.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_4_1_63,
      ADR3 => fifo_5_1_64,
      O => N7
    );
  Mmux_dmuxout_2_f6_0 : X_MUX2
    generic map(
      LOC => "CLB_R3C5.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f51_0,
      IB => Mmux_dmuxout_3_f51,
      SEL => rdptr(2),
      O => dmuxout(1)
    );
  Mmux_dmuxout_3_f5_1 : X_MUX2
    generic map(
      LOC => "CLB_R6C4.S1"
    )
    port map (
      IA => N11,
      IB => N10,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f52
    );
  Mmux_dmuxout_42 : X_LUT4
    generic map(
      INIT => X"CFC0",
      LOC => "CLB_R6C4.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_7_2_23,
      ADR2 => rdptr(0),
      ADR3 => fifo_6_2_12,
      O => N10
    );
  Mmux_dmuxout_54 : X_LUT4
    generic map(
      INIT => X"AFA0",
      LOC => "CLB_R6C4.S1"
    )
    port map (
      ADR0 => fifo_5_2_3,
      ADR1 => VCC,
      ADR2 => rdptr(0),
      ADR3 => fifo_4_2_65,
      O => N11
    );
  Mmux_dmuxout_2_f6_1 : X_MUX2
    generic map(
      LOC => "CLB_R6C4.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f52_0,
      IB => Mmux_dmuxout_3_f52,
      SEL => rdptr(2),
      O => dmuxout(2)
    );
  Mmux_dmuxout_3_f5_2 : X_MUX2
    generic map(
      LOC => "CLB_R5C6.S1"
    )
    port map (
      IA => N15,
      IB => N14,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f53
    );
  Mmux_dmuxout_43 : X_LUT4
    generic map(
      INIT => X"FA0A",
      LOC => "CLB_R5C6.S1"
    )
    port map (
      ADR0 => fifo_6_3_11,
      ADR1 => VCC,
      ADR2 => rdptr(0),
      ADR3 => fifo_7_3_22,
      O => N14
    );
  Mmux_dmuxout_56 : X_LUT4
    generic map(
      INIT => X"F0CC",
      LOC => "CLB_R5C6.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_4_3_66,
      ADR2 => fifo_5_3_2,
      ADR3 => rdptr(0),
      O => N15
    );
  Mmux_dmuxout_2_f6_2 : X_MUX2
    generic map(
      LOC => "CLB_R5C6.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f53_0,
      IB => Mmux_dmuxout_3_f53,
      SEL => rdptr(2),
      O => dmuxout(3)
    );
  wrptrclr_IMUX : X_BUF
    generic map(
      LOC => "PAD76"
    )
    port map (
      I => wrptrclr_IBUF_80,
      O => wrptrclr_IBUF_0
    );
  wrptrclr_IBUF : X_BUF
    generic map(
      LOC => "PAD76"
    )
    port map (
      I => wrptrclr,
      O => wrptrclr_IBUF_80
    );
  wrinc_IMUX : X_BUF
    generic map(
      LOC => "PAD77"
    )
    port map (
      I => wrinc_IBUF_81,
      O => wrinc_IBUF_0
    );
  wrinc_IBUF : X_BUF
    generic map(
      LOC => "PAD77"
    )
    port map (
      I => wrinc,
      O => wrinc_IBUF_81
    );
  rd_IMUX : X_BUF
    generic map(
      LOC => "PAD35"
    )
    port map (
      I => rd_IBUF_82,
      O => rd_IBUF_0
    );
  rd_IBUF : X_BUF
    generic map(
      LOC => "PAD35"
    )
    port map (
      I => rd,
      O => rd_IBUF_82
    );
  rdinc_IMUX : X_BUF
    generic map(
      LOC => "PAD93"
    )
    port map (
      I => rdinc_IBUF_83,
      O => rdinc_IBUF_0
    );
  rdinc_IBUF : X_BUF
    generic map(