fifo89_timesim.vhd

在ISE环境下用VHDL写的8*9FIFO

      LOC => "CLB_R4C3.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_5_8_17,
      ADR3 => fifo_4_8_10,
      O => N35
    );
  Mmux_dmuxout_2_f6_7 : X_MUX2
    generic map(
      LOC => "CLB_R4C3.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f58_0,
      IB => Mmux_dmuxout_3_f58,
      SEL => rdptr(2),
      O => dmuxout(8)
    );
  Mmux_dmuxout_4_f5 : X_MUX2
    generic map(
      LOC => "CLB_R4C7.S0"
    )
    port map (
      IA => N5,
      IB => N4,
      SEL => rdptr(1),
      O => Mmux_dmuxout_4_f5_74
    );
  Mmux_dmuxout_51 : X_LUT4
    generic map(
      INIT => X"EE22",
      LOC => "CLB_R4C7.S0"
    )
    port map (
      ADR0 => fifo_2_0_70,
      ADR1 => rdptr(0),
      ADR2 => VCC,
      ADR3 => fifo_3_0_71,
      O => N4
    );
  Mmux_dmuxout_6 : X_LUT4
    generic map(
      INIT => X"F3C0",
      LOC => "CLB_R4C7.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptr(0),
      ADR2 => fifo_1_0_72,
      ADR3 => fifo_0_0_30,
      O => N5
    );
  Mmux_dmuxout_4_f5_F5USED : X_BUF
    generic map(
      LOC => "CLB_R4C7.S0"
    )
    port map (
      I => Mmux_dmuxout_4_f5_74,
      O => Mmux_dmuxout_4_f5_0_67
    );
  wrptr_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C4.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => wrptr_1_FFY_RST
    );
  wrptr_0 : X_FF
    generic map(
      LOC => "CLB_R7C4.S1",
      INIT => '0'
    )
    port map (
      I => Mcount_wrptr,
      CE => wrptr_not0001,
      CLK => clk_BUFGP,
      SET => GND,
      RST => wrptr_1_FFY_RST,
      O => wrptr(0)
    );
  Mcount_wrptr_xor_1_11 : X_LUT4
    generic map(
      INIT => X"1212",
      LOC => "CLB_R7C4.S1"
    )
    port map (
      ADR0 => wrptr(0),
      ADR1 => wrptrclr_IBUF_0,
      ADR2 => wrptr(1),
      ADR3 => VCC,
      O => Mcount_wrptr3
    );
  Mcount_wrptr_xor_0_11 : X_LUT4
    generic map(
      INIT => X"0505",
      LOC => "CLB_R7C4.S1"
    )
    port map (
      ADR0 => wrptr(0),
      ADR1 => VCC,
      ADR2 => wrptrclr_IBUF_0,
      ADR3 => VCC,
      O => Mcount_wrptr
    );
  wrptr_not00011 : X_LUT4
    generic map(
      INIT => X"FCFC",
      LOC => "CLB_R7C5.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => wrinc_IBUF_0,
      ADR2 => wrptrclr_IBUF_0,
      ADR3 => VCC,
      O => wrptr_not0001_pack_1
    );
  Mcount_wrptr_xor_2_11 : X_LUT4
    generic map(
      INIT => X"060A",
      LOC => "CLB_R7C5.S1"
    )
    port map (
      ADR0 => wrptr(2),
      ADR1 => wrptr(0),
      ADR2 => wrptrclr_IBUF_0,
      ADR3 => wrptr(1),
      O => Mcount_wrptr6
    );
  wrptr_2_XUSED : X_BUF
    generic map(
      LOC => "CLB_R7C5.S1"
    )
    port map (
      I => wrptr_not0001_pack_1,
      O => wrptr_not0001
    );
  wrptr_2 : X_FF
    generic map(
      LOC => "CLB_R7C5.S1",
      INIT => '0'
    )
    port map (
      I => Mcount_wrptr6,
      CE => wrptr_not0001,
      CLK => clk_BUFGP,
      SET => GND,
      RST => wrptr_2_FFY_RST,
      O => wrptr(2)
    );
  wrptr_2_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C5.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => wrptr_2_FFY_RST
    );
  rdptr_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R2C4.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => rdptr_1_FFY_RST
    );
  rdptr_0 : X_FF
    generic map(
      LOC => "CLB_R2C4.S0",
      INIT => '0'
    )
    port map (
      I => Mcount_rdptr,
      CE => rdptr_not0001,
      CLK => clk_BUFGP,
      SET => GND,
      RST => rdptr_1_FFY_RST,
      O => rdptr(0)
    );
  Mcount_rdptr_xor_1_11 : X_LUT4
    generic map(
      INIT => X"1122",
      LOC => "CLB_R2C4.S0"
    )
    port map (
      ADR0 => rdptr(0),
      ADR1 => rdptrclr_IBUF_0,
      ADR2 => VCC,
      ADR3 => rdptr(1),
      O => Mcount_rdptr3
    );
  Mcount_rdptr_xor_0_11 : X_LUT4
    generic map(
      INIT => X"0303",
      LOC => "CLB_R2C4.S0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => rdptrclr_IBUF_0,
      ADR2 => rdptr(0),
      ADR3 => VCC,
      O => Mcount_rdptr
    );
  fifo_1_0 : X_FF
    generic map(
      LOC => "CLB_R4C4.S1",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_1_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_1_1_FFY_RST,
      O => fifo_1_0_72
    );
  fifo_1_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C4.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_1_1_FFY_RST
    );
  fifo_1_2 : X_FF
    generic map(
      LOC => "CLB_R6C5.S0",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_1_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_1_3_FFY_RST,
      O => fifo_1_2_44
    );
  fifo_1_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C5.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_1_3_FFY_RST
    );
  fifo_2_0 : X_FF
    generic map(
      LOC => "CLB_R3C6.S0",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_2_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_2_1_FFY_RST,
      O => fifo_2_0_70
    );
  fifo_2_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R3C6.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_2_1_FFY_RST
    );
  fifo_1_4 : X_FF
    generic map(
      LOC => "CLB_R6C9.S1",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,
      CE => fifo_1_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_1_5_FFY_RST,
      O => fifo_1_4_50
    );
  fifo_1_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C9.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_1_5_FFY_RST
    );
  fifo_2_2 : X_FF
    generic map(
      LOC => "CLB_R6C6.S0",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_2_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_2_3_FFY_RST,
      O => fifo_2_2_42
    );
  fifo_2_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C6.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_2_3_FFY_RST
    );
  fifo_1_6 : X_FF
    generic map(
      LOC => "CLB_R7C9.S1",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_1_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_1_7_FFY_RST,
      O => fifo_1_6_56
    );
  fifo_1_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C9.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_1_7_FFY_RST
    );
  fifo_3_0 : X_FF
    generic map(
      LOC => "CLB_R3C6.S1",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_3_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_3_1_FFY_RST,
      O => fifo_3_0_71
    );
  fifo_3_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R3C6.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_3_1_FFY_RST
    );
  fifo_2_4 : X_FF
    generic map(
      LOC => "CLB_R6C8.S0",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,
      CE => fifo_2_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_2_5_FFY_RST,
      O => fifo_2_4_48
    );
  fifo_2_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C8.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_2_5_FFY_RST
    );
  fifo_1_8 : X_FF
    generic map(
      LOC => "CLB_R6C3.S1",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_1_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_1_8_FFY_RST,
      O => fifo_1_8_62
    );
  fifo_1_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C3.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_1_8_FFY_RST
    );
  fifo_3_2 : X_FF
    generic map(
      LOC => "CLB_R6C6.S1",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_3_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_3_3_FFY_RST,
      O => fifo_3_2_43
    );
  fifo_3_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R6C6.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_3_3_FFY_RST
    );
  fifo_2_6 : X_FF
    generic map(
      LOC => "CLB_R7C6.S1",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_2_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_2_7_FFY_RST,
      O => fifo_2_6_54
    );
  fifo_2_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C6.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_2_7_FFY_RST
    );
  fifo_3_4 : X_FF
    generic map(
      LOC => "CLB_R7C6.S0",
      INIT => '0'
    )
    port map (
      I => data_in_4_IBUF_0,
      CE => fifo_3_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_3_5_FFY_RST,
      O => fifo_3_4_49
    );
  fifo_3_5_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R7C6.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_3_5_FFY_RST
    );
  fifo_2_8 : X_FF
    generic map(
      LOC => "CLB_R3C4.S0",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_2_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_2_8_FFY_RST,
      O => fifo_2_8_60
    );
  fifo_2_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R3C4.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_2_8_FFY_RST
    );
  fifo_4_0 : X_FF
    generic map(
      LOC => "CLB_R4C4.S0",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_1_FFY_RST,
      O => fifo_4_0_68
    );
  fifo_4_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C4.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_1_FFY_RST
    );
  fifo_3_6 : X_FF
    generic map(
      LOC => "CLB_R8C7.S1",
      INIT => '0'
    )
    port map (
      I => data_in_6_IBUF_0,
      CE => fifo_3_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_3_7_FFY_RST,
      O => fifo_3_6_55
    );
  fifo_3_7_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R8C7.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_3_7_FFY_RST
    );
  fifo_4_2 : X_FF
    generic map(
      LOC => "CLB_R5C4.S1",
      INIT => '0'
    )
    port map (
      I => data_in_2_IBUF_0,
      CE => fifo_4_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_4_3_FFY_RST,
      O => fifo_4_2_65
    );
  fifo_4_3_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C4.S1"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_4_3_FFY_RST
    );
  fifo_5_0 : X_FF
    generic map(
      LOC => "CLB_R5C3.S0",
      INIT => '0'
    )
    port map (
      I => data_in_0_IBUF_0,
      CE => fifo_5_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_5_1_FFY_RST,
      O => fifo_5_0_69
    );
  fifo_5_1_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R5C3.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_5_1_FFY_RST
    );
  fifo_3_8 : X_FF
    generic map(
      LOC => "CLB_R4C6.S0",
      INIT => '0'
    )
    port map (
      I => data_in_8_IBUF_0,
      CE => fifo_3_not0001_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => fifo_3_8_FFY_RST,
      O => fifo_3_8_61
    );
  fifo_3_8_FFY_RSTOR : X_BUF
    generic map(
      LOC => "CLB_R4C6.S0"
    )
    port map (
      I => rst_IBUF_0,
      O => fifo_3_8_FFY_RST
    );
  data_in_6_IMUX : X_BUF
    generic map(
      LOC => "PAD64"
    )
    port map (
      I => data_in_6_IBUF_75,
      O => data_in_6_IBUF_0
    );
  data_in_6_IBUF : X_BUF
    generic map(
      LOC => "PAD64"
    )
    port map (
      I => data_in(6),
      O => data_in_6_IBUF_75
    );
  data_in_6_DELAY : X_BUF
    generic map(
      LOC => "PAD64"
    )
    port map (
      I => data_in_6_IBUF_75,
      O => data_in_6_IDELAY
    );