fifo89_timesim.vhd

在ISE环境下用VHDL写的8*9FIFO

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: J.33
--  \   \         Application: netgen
--  /   /         Filename: fifo89_timesim.vhd
-- /___/   /\     Timestamp: Sat Dec 08 16:33:52 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 6 -pcf fifo89.pcf -rpw 100 -tpw 0 -ar Structure -tm fifo89 -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim fifo89.ncd fifo89_timesim.vhd 
-- Device	: 2s15cs144-6 (PRODUCTION 1.27 2006-10-19)
-- Input file	: fifo89.ncd
-- Output file	: F:\vhdl\fifos\fifo_exp1\netgen\par\fifo89_timesim.vhd
-- # of Entities	: 1
-- Design Name	: fifo89
-- Xilinx	: G:\Xilinx91i
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity fifo89 is
  port (
    clk : in STD_LOGIC := 'X'; 
    wrptrclr : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    rdinc : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    wrinc : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    rdptrclr : in STD_LOGIC := 'X'; 
    data_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 8 downto 0 ) 
  );
end fifo89;

architecture Structure of fifo89 is
  signal data_in_5_IBUF_0 : STD_LOGIC; 
  signal data_in_4_IBUF_0 : STD_LOGIC; 
  signal fifo_4_not0001_0 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal rst_IBUF_0 : STD_LOGIC; 
  signal fifo_4_5_0 : STD_LOGIC; 
  signal fifo_4_4_1 : STD_LOGIC; 
  signal data_in_3_IBUF_0 : STD_LOGIC; 
  signal data_in_2_IBUF_0 : STD_LOGIC; 
  signal fifo_5_not0001_0 : STD_LOGIC; 
  signal fifo_5_3_2 : STD_LOGIC; 
  signal fifo_5_2_3 : STD_LOGIC; 
  signal data_in_7_IBUF_0 : STD_LOGIC; 
  signal data_in_6_IBUF_0 : STD_LOGIC; 
  signal fifo_4_7_4 : STD_LOGIC; 
  signal fifo_4_6_5 : STD_LOGIC; 
  signal data_in_1_IBUF_0 : STD_LOGIC; 
  signal data_in_0_IBUF_0 : STD_LOGIC; 
  signal fifo_6_not0001_0 : STD_LOGIC; 
  signal fifo_6_1_6 : STD_LOGIC; 
  signal fifo_6_0_7 : STD_LOGIC; 
  signal fifo_5_5_8 : STD_LOGIC; 
  signal fifo_5_4_9 : STD_LOGIC; 
  signal data_in_8_IBUF_0 : STD_LOGIC; 
  signal fifo_4_8_10 : STD_LOGIC; 
  signal wr_IBUF_0 : STD_LOGIC; 
  signal fifo_0_not0001_0 : STD_LOGIC; 
  signal fifo_3_not0001_0 : STD_LOGIC; 
  signal fifo_6_3_11 : STD_LOGIC; 
  signal fifo_6_2_12 : STD_LOGIC; 
  signal fifo_5_7_13 : STD_LOGIC; 
  signal fifo_5_6_14 : STD_LOGIC; 
  signal fifo_6_5_15 : STD_LOGIC; 
  signal fifo_6_4_16 : STD_LOGIC; 
  signal fifo_5_8_17 : STD_LOGIC; 
  signal fifo_7_not0001_0 : STD_LOGIC; 
  signal fifo_7_1_18 : STD_LOGIC; 
  signal fifo_7_0_19 : STD_LOGIC; 
  signal fifo_6_7_20 : STD_LOGIC; 
  signal fifo_6_6_21 : STD_LOGIC; 
  signal fifo_7_3_22 : STD_LOGIC; 
  signal fifo_7_2_23 : STD_LOGIC; 
  signal fifo_1_not0001_0 : STD_LOGIC; 
  signal fifo_6_8_24 : STD_LOGIC; 
  signal fifo_7_5_25 : STD_LOGIC; 
  signal fifo_7_4_26 : STD_LOGIC; 
  signal fifo_7_7_27 : STD_LOGIC; 
  signal fifo_7_6_28 : STD_LOGIC; 
  signal fifo_7_8_29 : STD_LOGIC; 
  signal fifo_2_not0001_0 : STD_LOGIC; 
  signal rdptr_not0001 : STD_LOGIC; 
  signal rdptrclr_IBUF_0 : STD_LOGIC; 
  signal rdinc_IBUF_0 : STD_LOGIC; 
  signal wrptrclr_IBUF_0 : STD_LOGIC; 
  signal wrinc_IBUF_0 : STD_LOGIC; 
  signal rd_IBUF_0 : STD_LOGIC; 
  signal fifo_0_0_30 : STD_LOGIC; 
  signal fifo_0_1_31 : STD_LOGIC; 
  signal fifo_0_2_32 : STD_LOGIC; 
  signal fifo_0_3_33 : STD_LOGIC; 
  signal fifo_0_4_34 : STD_LOGIC; 
  signal fifo_0_5_35 : STD_LOGIC; 
  signal fifo_0_6_36 : STD_LOGIC; 
  signal fifo_0_7_37 : STD_LOGIC; 
  signal fifo_0_8_38 : STD_LOGIC; 
  signal fifo_2_1_39 : STD_LOGIC; 
  signal fifo_3_1_40 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f51_0 : STD_LOGIC; 
  signal fifo_1_1_41 : STD_LOGIC; 
  signal fifo_2_2_42 : STD_LOGIC; 
  signal fifo_3_2_43 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f52_0 : STD_LOGIC; 
  signal fifo_1_2_44 : STD_LOGIC; 
  signal fifo_2_3_45 : STD_LOGIC; 
  signal fifo_3_3_46 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f53_0 : STD_LOGIC; 
  signal fifo_1_3_47 : STD_LOGIC; 
  signal fifo_2_4_48 : STD_LOGIC; 
  signal fifo_3_4_49 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f54_0 : STD_LOGIC; 
  signal fifo_1_4_50 : STD_LOGIC; 
  signal fifo_2_5_51 : STD_LOGIC; 
  signal fifo_3_5_52 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f55_0 : STD_LOGIC; 
  signal fifo_1_5_53 : STD_LOGIC; 
  signal fifo_2_6_54 : STD_LOGIC; 
  signal fifo_3_6_55 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f56_0 : STD_LOGIC; 
  signal fifo_1_6_56 : STD_LOGIC; 
  signal fifo_2_7_57 : STD_LOGIC; 
  signal fifo_3_7_58 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f57_0 : STD_LOGIC; 
  signal fifo_1_7_59 : STD_LOGIC; 
  signal fifo_2_8_60 : STD_LOGIC; 
  signal fifo_3_8_61 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f58_0 : STD_LOGIC; 
  signal fifo_1_8_62 : STD_LOGIC; 
  signal fifo_4_1_63 : STD_LOGIC; 
  signal fifo_5_1_64 : STD_LOGIC; 
  signal fifo_4_2_65 : STD_LOGIC; 
  signal fifo_4_3_66 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f5_0_67 : STD_LOGIC; 
  signal fifo_4_0_68 : STD_LOGIC; 
  signal fifo_5_0_69 : STD_LOGIC; 
  signal fifo_2_0_70 : STD_LOGIC; 
  signal fifo_3_0_71 : STD_LOGIC; 
  signal fifo_1_0_72 : STD_LOGIC; 
  signal wrptr_not0001 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f54 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f55 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f56 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f5_73 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f57 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N35 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f58 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f5_74 : STD_LOGIC; 
  signal wrptr_1_FFY_RST : STD_LOGIC; 
  signal Mcount_wrptr3 : STD_LOGIC; 
  signal Mcount_wrptr : STD_LOGIC; 
  signal wrptr_not0001_pack_1 : STD_LOGIC; 
  signal Mcount_wrptr6 : STD_LOGIC; 
  signal wrptr_2_FFY_RST : STD_LOGIC; 
  signal rdptr_1_FFY_RST : STD_LOGIC; 
  signal Mcount_rdptr3 : STD_LOGIC; 
  signal Mcount_rdptr : STD_LOGIC; 
  signal fifo_1_1_FFY_RST : STD_LOGIC; 
  signal fifo_1_3_FFY_RST : STD_LOGIC; 
  signal fifo_2_1_FFY_RST : STD_LOGIC; 
  signal fifo_1_5_FFY_RST : STD_LOGIC; 
  signal fifo_2_3_FFY_RST : STD_LOGIC; 
  signal fifo_1_7_FFY_RST : STD_LOGIC; 
  signal fifo_3_1_FFY_RST : STD_LOGIC; 
  signal fifo_2_5_FFY_RST : STD_LOGIC; 
  signal fifo_1_8_FFY_RST : STD_LOGIC; 
  signal fifo_3_3_FFY_RST : STD_LOGIC; 
  signal fifo_2_7_FFY_RST : STD_LOGIC; 
  signal fifo_3_5_FFY_RST : STD_LOGIC; 
  signal fifo_2_8_FFY_RST : STD_LOGIC; 
  signal fifo_4_1_FFY_RST : STD_LOGIC; 
  signal fifo_3_7_FFY_RST : STD_LOGIC; 
  signal fifo_4_3_FFY_RST : STD_LOGIC; 
  signal fifo_5_1_FFY_RST : STD_LOGIC; 
  signal fifo_3_8_FFY_RST : STD_LOGIC; 
  signal data_in_6_IDELAY : STD_LOGIC; 
  signal data_in_6_IBUF_75 : STD_LOGIC; 
  signal data_in_7_IDELAY : STD_LOGIC; 
  signal data_in_7_IBUF_76 : STD_LOGIC; 
  signal data_in_8_IDELAY : STD_LOGIC; 
  signal data_in_8_IBUF_77 : STD_LOGIC; 
  signal rdptrclr_IBUF_78 : STD_LOGIC; 
  signal rst_IBUF_79 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f51 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f52 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N17 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f53 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N211 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f54 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f55 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f56 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f57 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N37 : STD_LOGIC; 
  signal Mmux_dmuxout_4_f58 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f51 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f52 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal Mmux_dmuxout_3_f53 : STD_LOGIC; 
  signal wrptrclr_IBUF_80 : STD_LOGIC; 
  signal wrinc_IBUF_81 : STD_LOGIC; 
  signal rd_IBUF_82 : STD_LOGIC; 
  signal rdinc_IBUF_83 : STD_LOGIC; 
  signal wr_IBUF_84 : STD_LOGIC; 
  signal data_out_0_TORGTS : STD_LOGIC; 
  signal data_out_0_OUTMUX_85 : STD_LOGIC; 
  signal data_out_1_TORGTS : STD_LOGIC; 
  signal data_out_1_OUTMUX_86 : STD_LOGIC; 
  signal data_out_2_TORGTS : STD_LOGIC; 
  signal data_out_2_OUTMUX_87 : STD_LOGIC; 
  signal data_out_3_TORGTS : STD_LOGIC; 
  signal data_out_3_OUTMUX_88 : STD_LOGIC; 
  signal data_out_4_TORGTS : STD_LOGIC; 
  signal data_out_4_OUTMUX_89 : STD_LOGIC; 
  signal data_in_0_IDELAY : STD_LOGIC; 
  signal data_in_0_IBUF_90 : STD_LOGIC; 
  signal data_out_5_TORGTS : STD_LOGIC; 
  signal data_out_5_OUTMUX_91 : STD_LOGIC; 
  signal data_in_1_IDELAY : STD_LOGIC; 
  signal data_in_1_IBUF_92 : STD_LOGIC; 
  signal data_out_6_TORGTS : STD_LOGIC; 
  signal data_out_6_OUTMUX_93 : STD_LOGIC; 
  signal data_in_2_IDELAY : STD_LOGIC; 
  signal data_in_2_IBUF_94 : STD_LOGIC; 
  signal data_out_7_TORGTS : STD_LOGIC; 
  signal data_out_7_OUTMUX_95 : STD_LOGIC; 
  signal data_in_3_IDELAY : STD_LOGIC; 
  signal data_in_3_IBUF_96 : STD_LOGIC; 
  signal data_out_8_TORGTS : STD_LOGIC; 
  signal data_out_8_OUTMUX_97 : STD_LOGIC; 
  signal data_in_4_IDELAY : STD_LOGIC; 
  signal data_in_4_IBUF_98 : STD_LOGIC; 
  signal data_in_5_IDELAY : STD_LOGIC; 
  signal data_in_5_IBUF_99 : STD_LOGIC; 
  signal fifo_4_5_FFY_RST : STD_LOGIC; 
  signal fifo_5_3_FFY_RST : STD_LOGIC; 
  signal fifo_4_7_FFY_RST : STD_LOGIC; 
  signal fifo_6_1_FFY_RST : STD_LOGIC; 
  signal fifo_5_5_FFY_RST : STD_LOGIC; 
  signal fifo_4_8_FFY_RST : STD_LOGIC; 
  signal fifo_0_not0001 : STD_LOGIC; 
  signal fifo_3_not0001 : STD_LOGIC; 
  signal fifo_6_3_FFY_RST : STD_LOGIC; 
  signal fifo_5_7_FFY_RST : STD_LOGIC; 
  signal fifo_6_5_FFY_RST : STD_LOGIC; 
  signal fifo_5_8_FFY_RST : STD_LOGIC; 
  signal fifo_7_1_FFY_RST : STD_LOGIC; 
  signal fifo_6_7_FFY_RST : STD_LOGIC; 
  signal fifo_7_3_FFY_RST : STD_LOGIC; 
  signal fifo_1_not0001 : STD_LOGIC; 
  signal fifo_4_not0001 : STD_LOGIC; 
  signal fifo_6_8_FFY_RST : STD_LOGIC; 
  signal fifo_7_5_FFY_RST : STD_LOGIC; 
  signal fifo_7_7_FFY_RST : STD_LOGIC; 
  signal fifo_7_8_FFY_RST : STD_LOGIC; 
  signal fifo_2_not0001 : STD_LOGIC; 
  signal fifo_5_not0001 : STD_LOGIC; 
  signal fifo_7_not0001 : STD_LOGIC; 
  signal fifo_6_not0001 : STD_LOGIC; 
  signal Mcount_rdptr6 : STD_LOGIC; 
  signal rdptr_not0001_pack_1 : STD_LOGIC; 
  signal rdptr_2_FFX_RST : STD_LOGIC; 
  signal fifo_4_5_FFX_RST : STD_LOGIC; 
  signal fifo_5_3_FFX_RST : STD_LOGIC; 
  signal fifo_4_7_FFX_RST : STD_LOGIC; 
  signal fifo_6_1_FFX_RST : STD_LOGIC; 
  signal fifo_5_5_FFX_RST : STD_LOGIC; 
  signal fifo_6_3_FFX_RST : STD_LOGIC; 
  signal fifo_5_7_FFX_RST : STD_LOGIC; 
  signal fifo_6_5_FFX_RST : STD_LOGIC; 
  signal fifo_7_1_FFX_RST : STD_LOGIC; 
  signal fifo_6_7_FFX_RST : STD_LOGIC; 
  signal wrptr_1_FFX_RST : STD_LOGIC; 
  signal rdptr_1_FFX_RST : STD_LOGIC; 
  signal data_in_0_IFF_RST : STD_LOGIC; 
  signal data_in_1_IFF_RST : STD_LOGIC; 
  signal data_in_2_IFF_RST : STD_LOGIC; 
  signal data_in_3_IFF_RST : STD_LOGIC; 
  signal data_in_4_IFF_RST : STD_LOGIC; 
  signal data_in_5_IFF_RST : STD_LOGIC; 
  signal data_in_6_IFF_RST : STD_LOGIC; 
  signal data_in_7_IFF_RST : STD_LOGIC; 
  signal data_in_8_IFF_RST : STD_LOGIC; 
  signal fifo_7_3_FFX_RST : STD_LOGIC; 
  signal fifo_7_5_FFX_RST : STD_LOGIC; 
  signal fifo_7_7_FFX_RST : STD_LOGIC; 
  signal fifo_1_1_FFX_RST : STD_LOGIC; 
  signal fifo_1_3_FFX_RST : STD_LOGIC; 
  signal fifo_2_1_FFX_RST : STD_LOGIC; 
  signal fifo_1_5_FFX_RST : STD_LOGIC; 
  signal fifo_2_3_FFX_RST : STD_LOGIC; 
  signal fifo_1_7_FFX_RST : STD_LOGIC; 
  signal fifo_3_1_FFX_RST : STD_LOGIC; 
  signal fifo_2_5_FFX_RST : STD_LOGIC; 
  signal fifo_3_3_FFX_RST : STD_LOGIC; 
  signal fifo_2_7_FFX_RST : STD_LOGIC; 
  signal fifo_3_5_FFX_RST : STD_LOGIC; 
  signal fifo_4_1_FFX_RST : STD_LOGIC; 
  signal fifo_3_7_FFX_RST : STD_LOGIC; 
  signal fifo_4_3_FFX_RST : STD_LOGIC; 
  signal fifo_5_1_FFX_RST : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal wrptr : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal rdptr : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal dmuxout : STD_LOGIC_VECTOR ( 8 downto 0 ); 
begin
  Mmux_dmuxout_3_f5_3 : X_MUX2
    generic map(
      LOC => "CLB_R6C7.S1"
    )
    port map (
      IA => N19,
      IB => N18,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f54
    );
  Mmux_dmuxout_44 : X_LUT4
    generic map(
      INIT => X"FA0A",
      LOC => "CLB_R6C7.S1"
    )
    port map (
      ADR0 => fifo_6_4_16,
      ADR1 => VCC,
      ADR2 => rdptr(0),
      ADR3 => fifo_7_4_26,
      O => N18
    );
  Mmux_dmuxout_58 : X_LUT4
    generic map(
      INIT => X"FC0C",
      LOC => "CLB_R6C7.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_4_4_1,
      ADR2 => rdptr(0),
      ADR3 => fifo_5_4_9,
      O => N19
    );
  Mmux_dmuxout_2_f6_3 : X_MUX2
    generic map(
      LOC => "CLB_R6C7.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f54_0,
      IB => Mmux_dmuxout_3_f54,
      SEL => rdptr(2),
      O => dmuxout(4)
    );
  Mmux_dmuxout_3_f5_4 : X_MUX2
    generic map(
      LOC => "CLB_R5C8.S1"
    )
    port map (
      IA => N23,
      IB => N22,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f55
    );
  Mmux_dmuxout_45 : X_LUT4
    generic map(
      INIT => X"F0AA",
      LOC => "CLB_R5C8.S1"
    )
    port map (
      ADR0 => fifo_6_5_15,
      ADR1 => VCC,
      ADR2 => fifo_7_5_25,
      ADR3 => rdptr(0),
      O => N22
    );
  Mmux_dmuxout_510 : X_LUT4
    generic map(
      INIT => X"F0AA",
      LOC => "CLB_R5C8.S1"
    )
    port map (
      ADR0 => fifo_4_5_0,
      ADR1 => VCC,
      ADR2 => fifo_5_5_8,
      ADR3 => rdptr(0),
      O => N23
    );
  Mmux_dmuxout_2_f6_4 : X_MUX2
    generic map(
      LOC => "CLB_R5C8.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f55_0,
      IB => Mmux_dmuxout_3_f55,
      SEL => rdptr(2),
      O => dmuxout(5)
    );
  Mmux_dmuxout_3_f5_5 : X_MUX2
    generic map(
      LOC => "CLB_R8C8.S1"
    )
    port map (
      IA => N27,
      IB => N26,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f56
    );
  Mmux_dmuxout_46 : X_LUT4
    generic map(
      INIT => X"E2E2",
      LOC => "CLB_R8C8.S1"
    )
    port map (
      ADR0 => fifo_6_6_21,
      ADR1 => rdptr(0),
      ADR2 => fifo_7_6_28,
      ADR3 => VCC,
      O => N26
    );
  Mmux_dmuxout_512 : X_LUT4
    generic map(
      INIT => X"AACC",
      LOC => "CLB_R8C8.S1"
    )
    port map (
      ADR0 => fifo_5_6_14,
      ADR1 => fifo_4_6_5,
      ADR2 => VCC,
      ADR3 => rdptr(0),
      O => N27
    );
  Mmux_dmuxout_2_f6_5 : X_MUX2
    generic map(
      LOC => "CLB_R8C8.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f56_0,
      IB => Mmux_dmuxout_3_f56,
      SEL => rdptr(2),
      O => dmuxout(6)
    );
  Mmux_dmuxout_3_f5 : X_MUX2
    generic map(
      LOC => "CLB_R4C7.S1"
    )
    port map (
      IA => N3,
      IB => N21,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f5_73
    );
  Mmux_dmuxout_4 : X_LUT4
    generic map(
      INIT => X"FA0A",
      LOC => "CLB_R4C7.S1"
    )
    port map (
      ADR0 => fifo_6_0_7,
      ADR1 => VCC,
      ADR2 => rdptr(0),
      ADR3 => fifo_7_0_19,
      O => N21
    );
  Mmux_dmuxout_5 : X_LUT4
    generic map(
      INIT => X"F0CC",
      LOC => "CLB_R4C7.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_4_0_68,
      ADR2 => fifo_5_0_69,
      ADR3 => rdptr(0),
      O => N3
    );
  Mmux_dmuxout_2_f6 : X_MUX2
    generic map(
      LOC => "CLB_R4C7.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f5_0_67,
      IB => Mmux_dmuxout_3_f5_73,
      SEL => rdptr(2),
      O => dmuxout(0)
    );
  Mmux_dmuxout_3_f5_6 : X_MUX2
    generic map(
      LOC => "CLB_R7C7.S1"
    )
    port map (
      IA => N31,
      IB => N30,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f57
    );
  Mmux_dmuxout_47 : X_LUT4
    generic map(
      INIT => X"ACAC",
      LOC => "CLB_R7C7.S1"
    )
    port map (
      ADR0 => fifo_7_7_27,
      ADR1 => fifo_6_7_20,
      ADR2 => rdptr(0),
      ADR3 => VCC,
      O => N30
    );
  Mmux_dmuxout_514 : X_LUT4
    generic map(
      INIT => X"FC0C",
      LOC => "CLB_R7C7.S1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => fifo_4_7_4,
      ADR2 => rdptr(0),
      ADR3 => fifo_5_7_13,
      O => N31
    );
  Mmux_dmuxout_2_f6_6 : X_MUX2
    generic map(
      LOC => "CLB_R7C7.S1"
    )
    port map (
      IA => Mmux_dmuxout_4_f57_0,
      IB => Mmux_dmuxout_3_f57,
      SEL => rdptr(2),
      O => dmuxout(7)
    );
  Mmux_dmuxout_3_f5_7 : X_MUX2
    generic map(
      LOC => "CLB_R4C3.S1"
    )
    port map (
      IA => N35,
      IB => N34,
      SEL => rdptr(1),
      O => Mmux_dmuxout_3_f58
    );
  Mmux_dmuxout_48 : X_LUT4
    generic map(
      INIT => X"FA0A",
      LOC => "CLB_R4C3.S1"
    )
    port map (
      ADR0 => fifo_6_8_24,
      ADR1 => VCC,
      ADR2 => rdptr(0),
      ADR3 => fifo_7_8_29,
      O => N34
    );
  Mmux_dmuxout_516 : X_LUT4
    generic map(
      INIT => X"F3C0",