fifo89.gyd

在ISE环境下用VHDL写的8*9FIFO

Pin Freeze File:  version J.33

3128XL100 XCR3128XL-6-VQ100
clk S:PIN90
data_in<0> S:PIN72
data_in<1> S:PIN71
data_in<2> S:PIN70
data_in<3> S:PIN69
data_in<4> S:PIN68
data_in<5> S:PIN67
data_in<6> S:PIN65
data_in<7> S:PIN64
data_in<8> S:PIN63
rd S:PIN79
rdinc S:PIN80
rdptrclr S:PIN81
rst S:PIN83
wr S:PIN41
wrinc S:PIN42
wrptrclr S:PIN44
data_out<0> S:PIN75
data_out<1> S:PIN76
data_out<2> S:PIN77
data_out<3> S:PIN78
data_out<4> S:PIN61
data_out<5> S:PIN60
data_out<6> S:PIN58
data_out<7> S:PIN57
data_out<8> S:PIN40


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_1 fifo_7_0 fifo_1_0 fifo_0_0 fifo_0_1
		 fifo_0_2 fifo_0_3 fifo_0_4 fifo_6_0
		 fifo_5_0 fifo_4_0 fifo_0_5 fifo_3_0
		 fifo_0_6 fifo_0_7 fifo_0_8 fifo_2_0
		
PARTITION FB2_1 data_out<0> data_out<1> data_out<2> data_out<3>
		
PARTITION FB2_14 rdptr<0> rdptr<1> rdptr<2>
PARTITION FB3_2 wrptr<0> data_out<4> data_out<5>
PARTITION FB3_6 data_out<6> data_out<7>

PARTITION FB4_1 fifo_4_1 data_out<8> fifo_6_2 fifo_5_2
		 fifo_4_2 fifo_3_2 fifo_2_2 fifo_3_1
		 fifo_2_1 fifo_1_1 fifo_1_2 fifo_7_1
		 fifo_6_1 fifo_5_1 wrptr<2> wrptr<1>
		
PARTITION FB5_1 fifo_2_5 fifo_1_5 fifo_7_4 fifo_6_4
		 fifo_5_4 fifo_4_4 fifo_3_4 fifo_6_3
		 fifo_5_3 fifo_4_3 fifo_3_3 fifo_2_3
		 fifo_2_4 fifo_1_4 fifo_7_3 fifo_1_3
		
PARTITION FB6_1 fifo_7_6 fifo_1_6 fifo_2_8 fifo_1_8
		 fifo_7_7 fifo_6_7 fifo_5_7 fifo_6_6
		 fifo_5_6 fifo_4_6 fifo_4_7 fifo_3_6
		 fifo_2_6 fifo_3_7 fifo_2_7 fifo_1_7
		
PARTITION FB7_1 fifo_3_8
PARTITION FB7_7 fifo_7_2 fifo_7_5 fifo_6_5 fifo_5_5
		 fifo_7_8 fifo_6_8 fifo_5_8 fifo_4_8
		 fifo_4_5 fifo_3_5