fifo89_preroute.twr

在ISE环境下用VHDL写的8*9FIFO

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Release 9.1.03i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

G:\Xilinx91i\bin\nt\trce.exe -ise F:/vhdl/fifos/fifo_exp1/fifo_exp1.ise
-intstyle ise -e 3 -s 6 -xml fifo89_preroute fifo89_map.ncd -o
fifo89_preroute.twr fifo89.pcf -ucf fifo89.ucf

Design file:              fifo89_map.ncd
Physical constraint file: fifo89.pcf
Device,package,speed:     xc2s15,cs144,-6 (PRODUCTION 1.27 2006-10-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay 
   information.  For accurate numbers, please refer to the post Place and Route 
   timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data_in<0>  |    2.082(R)|    0.508(R)|clk_BUFGP         |   0.000|
data_in<1>  |    2.082(R)|    0.555(R)|clk_BUFGP         |   0.000|
data_in<2>  |    2.082(R)|    0.508(R)|clk_BUFGP         |   0.000|
data_in<3>  |    2.082(R)|    0.555(R)|clk_BUFGP         |   0.000|
data_in<4>  |    2.082(R)|    0.508(R)|clk_BUFGP         |   0.000|
data_in<5>  |    2.082(R)|    0.555(R)|clk_BUFGP         |   0.000|
data_in<6>  |    2.082(R)|    0.508(R)|clk_BUFGP         |   0.000|
data_in<7>  |    2.082(R)|    0.555(R)|clk_BUFGP         |   0.000|
data_in<8>  |    2.082(R)|    0.508(R)|clk_BUFGP         |   0.000|
rdinc       |    0.905(R)|   -0.019(R)|clk_BUFGP         |   0.000|
rdptrclr    |    0.905(R)|    0.202(R)|clk_BUFGP         |   0.000|
wr          |    0.905(R)|   -0.018(R)|clk_BUFGP         |   0.000|
wrinc       |    0.905(R)|   -0.019(R)|clk_BUFGP         |   0.000|
wrptrclr    |    0.905(R)|    0.202(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
data_out<0> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<1> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<2> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<3> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<4> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<5> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<6> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<7> |    9.001(R)|clk_BUFGP         |   0.000|
data_out<8> |    9.001(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    2.892|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
rd             |data_out<0>    |    5.769|
rd             |data_out<1>    |    5.769|
rd             |data_out<2>    |    5.769|
rd             |data_out<3>    |    5.769|
rd             |data_out<4>    |    5.769|
rd             |data_out<5>    |    5.769|
rd             |data_out<6>    |    5.769|
rd             |data_out<7>    |    5.769|
rd             |data_out<8>    |    5.769|
---------------+---------------+---------+


Analysis completed Sat Dec 08 16:35:48 2007 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 70 MB