fifo89.syr

在ISE环境下用VHDL写的8*9FIFO

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fifo89.ngr
Top Level Output File Name         : fifo89
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Cell Usage :
# BELS                             : 80
#      INV                         : 1
#      LUT2                        : 4
#      LUT3                        : 38
#      LUT4                        : 10
#      MUXF5                       : 18
#      MUXF6                       : 9
# FlipFlops/Latches                : 78
#      FDCE                        : 78
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 16
#      OBUFT                       : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s15cs144-6 

 Number of Slices:                      65  out of    192    33%  
 Number of Slice Flip Flops:            78  out of    384    20%  
 Number of 4 input LUTs:                53  out of    384    13%  
 Number of IOs:                         26
 Number of bonded IOBs:                 26  out of     86    30%  
 Number of GCLKs:                        1  out of      4    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 78    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
rst                                | IBUF                   | 78    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.498ns (Maximum Frequency: 153.894MHz)
   Minimum input arrival time before clock: 5.964ns
   Maximum output required time after clock: 11.703ns
   Maximum combinational path delay: 9.075ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.498ns (frequency: 153.894MHz)
  Total number of paths / destination ports: 228 / 78
-------------------------------------------------------------------------
Delay:               6.498ns (Levels of Logic = 1)
  Source:            wrptr_0 (FF)
  Destination:       fifo_0_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: wrptr_0 to fifo_0_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            11   1.085   2.070  wrptr_0 (wrptr_0)
     LUT4:I2->O            9   0.549   1.908  fifo_7_not00011 (fifo_7_not0001)
     FDCE:CE                   0.886          fifo_7_0
    ----------------------------------------
    Total                      6.498ns (2.520ns logic, 3.978ns route)
                                       (38.8% logic, 61.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 162 / 156
-------------------------------------------------------------------------
Offset:              5.964ns (Levels of Logic = 2)
  Source:            wr (PAD)
  Destination:       fifo_0_0 (FF)
  Destination Clock: clk rising

  Data Path: wr to fifo_0_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.776   1.845  wr_IBUF (wr_IBUF)
     LUT4:I0->O            9   0.549   1.908  fifo_7_not00011 (fifo_7_not0001)
     FDCE:CE                   0.886          fifo_7_0
    ----------------------------------------
    Total                      5.964ns (2.211ns logic, 3.753ns route)
                                       (37.1% logic, 62.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 135 / 9
-------------------------------------------------------------------------
Offset:              11.703ns (Levels of Logic = 4)
  Source:            rdptr_0 (FF)
  Destination:       data_out<8> (PAD)
  Source Clock:      clk rising

  Data Path: rdptr_0 to data_out<8>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            39   1.085   3.735  rdptr_0 (rdptr_0)
     LUT3:I0->O            1   0.549   0.000  Mmux_dmuxout_6 (N5)
     MUXF5:I0->O           1   0.315   0.000  Mmux_dmuxout_4_f5 (Mmux_dmuxout_4_f5)
     MUXF6:I0->O           1   0.316   1.035  Mmux_dmuxout_2_f6 (dmuxout<0>)
     OBUFT:I->O                4.668          data_out_0_OBUFT (data_out<0>)
    ----------------------------------------
    Total                     11.703ns (6.933ns logic, 4.770ns route)
                                       (59.2% logic, 40.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Delay:               9.075ns (Levels of Logic = 3)
  Source:            rd (PAD)
  Destination:       data_out<8> (PAD)

  Data Path: rd to data_out<8>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  rd_IBUF (rd_IBUF)
     INV:I->O              9   0.549   1.908  rd_inv1_INV_0 (rd_inv)
     OBUFT:T->O                4.807          data_out_8_OBUFT (data_out<8>)
    ----------------------------------------
    Total                      9.075ns (6.132ns logic, 2.943ns route)
                                       (67.6% logic, 32.4% route)

=========================================================================
CPU : 5.80 / 6.36 s | Elapsed : 5.00 / 6.00 s
 
--> 

Total memory usage is 128888 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)