fifo89.syr

在ISE环境下用VHDL写的8*9FIFO

Release 9.1.03i - xst J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: fifo89.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "fifo89.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "fifo89"
Output Format                      : NGC
Target Device                      : xc2s15-6-cs144

---- Source Options
Top Module Name                    : fifo89
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Convert Tristates To Logic         : Yes
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : fifo89.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/vhdl/fifos/fifo_exp1/fifo_exp1.vhd" in Library work.
Architecture behavioral of Entity fifo89 is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <fifo89> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <fifo89> in library <work> (Architecture <behavioral>).
Entity <fifo89> analyzed. Unit <fifo89> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <fifo89>.
    Related source file is "F:/vhdl/fifos/fifo_exp1/fifo_exp1.vhd".
    Found 9-bit tristate buffer for signal <data_out>.
    Found 9-bit 8-to-1 multiplexer for signal <dmuxout>.
    Found 1-of-8 decoder for signal <en>.
    Found 72-bit register for signal <fifo>.
    Found 3-bit up counter for signal <rdptr>.
    Found 3-bit up counter for signal <wrptr>.
    Summary:
	inferred   2 Counter(s).
	inferred  72 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
	inferred   1 Decoder(s).
	inferred   9 Tristate(s).
Unit <fifo89> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 3-bit up counter                                      : 2
# Registers                                            : 8
 9-bit register                                        : 8
# Multiplexers                                         : 1
 9-bit 8-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-8 decoder                                        : 1
# Tristates                                            : 1
 9-bit tristate buffer                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2s15.nph' in environment G:\Xilinx91i.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 3-bit up counter                                      : 2
# Registers                                            : 72
 Flip-Flops                                            : 72
# Multiplexers                                         : 1
 9-bit 8-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-8 decoder                                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fifo89> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fifo89, actual ratio is 33.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 78
 Flip-Flops                                            : 78