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<br/> fifo_2_5_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_2_6: FDCPE port map (fifo_2_6,data_in(6),clk,rst,'0',fifo_2_6_CE);
<br/> fifo_2_6_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_2_7: FDCPE port map (fifo_2_7,data_in(7),clk,rst,'0',fifo_2_7_CE);
<br/> fifo_2_7_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_2_8: FDCPE port map (fifo_2_8,data_in(8),clk,rst,'0',fifo_2_8_CE);
<br/> fifo_2_8_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_0: FDCPE port map (fifo_3_0,data_in(0),clk,rst,'0',fifo_3_0_CE);
<br/> fifo_3_0_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_1: FDCPE port map (fifo_3_1,data_in(1),clk,rst,'0',fifo_3_1_CE);
<br/> fifo_3_1_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_2: FDCPE port map (fifo_3_2,data_in(2),clk,rst,'0',fifo_3_2_CE);
<br/> fifo_3_2_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_3: FDCPE port map (fifo_3_3,data_in(3),clk,rst,'0',fifo_3_3_CE);
<br/> fifo_3_3_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_4: FDCPE port map (fifo_3_4,data_in(4),clk,rst,'0',fifo_3_4_CE);
<br/> fifo_3_4_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_5: FDCPE port map (fifo_3_5,data_in(5),clk,rst,'0',fifo_3_5_CE);
<br/> fifo_3_5_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_6: FDCPE port map (fifo_3_6,data_in(6),clk,rst,'0',fifo_3_6_CE);
<br/> fifo_3_6_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_7: FDCPE port map (fifo_3_7,data_in(7),clk,rst,'0',fifo_3_7_CE);
<br/> fifo_3_7_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_3_8: FDCPE port map (fifo_3_8,data_in(8),clk,rst,'0',fifo_3_8_CE);
<br/> fifo_3_8_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_0: FDCPE port map (fifo_4_0,data_in(0),clk,rst,'0',fifo_4_0_CE);
<br/> fifo_4_0_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_1: FDCPE port map (fifo_4_1,data_in(1),clk,rst,'0',fifo_4_1_CE);
<br/> fifo_4_1_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_2: FDCPE port map (fifo_4_2,data_in(2),clk,rst,'0',fifo_4_2_CE);
<br/> fifo_4_2_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_3: FDCPE port map (fifo_4_3,data_in(3),clk,rst,'0',fifo_4_3_CE);
<br/> fifo_4_3_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_4: FDCPE port map (fifo_4_4,data_in(4),clk,rst,'0',fifo_4_4_CE);
<br/> fifo_4_4_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_5: FDCPE port map (fifo_4_5,data_in(5),clk,rst,'0',fifo_4_5_CE);
<br/> fifo_4_5_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_6: FDCPE port map (fifo_4_6,data_in(6),clk,rst,'0',fifo_4_6_CE);
<br/> fifo_4_6_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_7: FDCPE port map (fifo_4_7,data_in(7),clk,rst,'0',fifo_4_7_CE);
<br/> fifo_4_7_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_4_8: FDCPE port map (fifo_4_8,data_in(8),clk,rst,'0',fifo_4_8_CE);
<br/> fifo_4_8_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_0: FDCPE port map (fifo_5_0,data_in(0),clk,rst,'0',fifo_5_0_CE);
<br/> fifo_5_0_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_1: FDCPE port map (fifo_5_1,data_in(1),clk,rst,'0',fifo_5_1_CE);
<br/> fifo_5_1_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_2: FDCPE port map (fifo_5_2,data_in(2),clk,rst,'0',fifo_5_2_CE);
<br/> fifo_5_2_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_3: FDCPE port map (fifo_5_3,data_in(3),clk,rst,'0',fifo_5_3_CE);
<br/> fifo_5_3_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_4: FDCPE port map (fifo_5_4,data_in(4),clk,rst,'0',fifo_5_4_CE);
<br/> fifo_5_4_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_5: FDCPE port map (fifo_5_5,data_in(5),clk,rst,'0',fifo_5_5_CE);
<br/> fifo_5_5_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_6: FDCPE port map (fifo_5_6,data_in(6),clk,rst,'0',fifo_5_6_CE);
<br/> fifo_5_6_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_7: FDCPE port map (fifo_5_7,data_in(7),clk,rst,'0',fifo_5_7_CE);
<br/> fifo_5_7_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_5_8: FDCPE port map (fifo_5_8,data_in(8),clk,rst,'0',fifo_5_8_CE);
<br/> fifo_5_8_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_0: FDCPE port map (fifo_6_0,data_in(0),clk,rst,'0',fifo_6_0_CE);
<br/> fifo_6_0_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_1: FDCPE port map (fifo_6_1,data_in(1),clk,rst,'0',fifo_6_1_CE);
<br/> fifo_6_1_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_2: FDCPE port map (fifo_6_2,data_in(2),clk,rst,'0',fifo_6_2_CE);
<br/> fifo_6_2_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_3: FDCPE port map (fifo_6_3,data_in(3),clk,rst,'0',fifo_6_3_CE);
<br/> fifo_6_3_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_4: FDCPE port map (fifo_6_4,data_in(4),clk,rst,'0',fifo_6_4_CE);
<br/> fifo_6_4_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_5: FDCPE port map (fifo_6_5,data_in(5),clk,rst,'0',fifo_6_5_CE);
<br/> fifo_6_5_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_6: FDCPE port map (fifo_6_6,data_in(6),clk,rst,'0',fifo_6_6_CE);
<br/> fifo_6_6_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_7: FDCPE port map (fifo_6_7,data_in(7),clk,rst,'0',fifo_6_7_CE);
<br/> fifo_6_7_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_6_8: FDCPE port map (fifo_6_8,data_in(8),clk,rst,'0',fifo_6_8_CE);
<br/> fifo_6_8_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_0: FDCPE port map (fifo_7_0,data_in(0),clk,rst,'0',fifo_7_0_CE);
<br/> fifo_7_0_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_1: FDCPE port map (fifo_7_1,data_in(1),clk,rst,'0',fifo_7_1_CE);
<br/> fifo_7_1_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_2: FDCPE port map (fifo_7_2,data_in(2),clk,rst,'0',fifo_7_2_CE);
<br/> fifo_7_2_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_3: FDCPE port map (fifo_7_3,data_in(3),clk,rst,'0',fifo_7_3_CE);
<br/> fifo_7_3_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_4: FDCPE port map (fifo_7_4,data_in(4),clk,rst,'0',fifo_7_4_CE);
<br/> fifo_7_4_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_5: FDCPE port map (fifo_7_5,data_in(5),clk,rst,'0',fifo_7_5_CE);
<br/> fifo_7_5_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_6: FDCPE port map (fifo_7_6,data_in(6),clk,rst,'0',fifo_7_6_CE);
<br/> fifo_7_6_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_7: FDCPE port map (fifo_7_7,data_in(7),clk,rst,'0',fifo_7_7_CE);
<br/> fifo_7_7_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_7_8: FDCPE port map (fifo_7_8,data_in(8),clk,rst,'0',fifo_7_8_CE);
<br/> fifo_7_8_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
</td></tr><tr><td>
FDCPE_rdptr0: FDCPE port map (rdptr(0),rdptr_D(0),clk,rst,'0','1');
<br/> rdptr_D(0) <= ((NOT rdptrclr AND rdinc AND NOT rdptr(0))
<br/> OR (NOT rdptrclr AND NOT rdinc AND rdptr(0)));
</td></tr><tr><td>
FTCPE_rdptr1: FTCPE port map (rdptr(1),rdptr_T(1),clk,rst,'0','1');
<br/> rdptr_T(1) <= ((rdptrclr AND rdptr(1))
<br/> OR (NOT rdptrclr AND rdinc AND rdptr(0)));
</td></tr><tr><td>
FTCPE_rdptr2: FTCPE port map (rdptr(2),rdptr_T(2),clk,rst,'0','1');
<br/> rdptr_T(2) <= ((rdptr(2) AND rdptrclr)
<br/> OR (NOT rdptrclr AND rdinc AND rdptr(1) AND rdptr(0)));
</td></tr><tr><td>
FDCPE_wrptr0: FDCPE port map (wrptr(0),wrptr_D(0),clk,rst,'0','1');
<br/> wrptr_D(0) <= ((wrptr(0) AND NOT wrptrclr AND NOT wrinc)
<br/> OR (NOT wrptr(0) AND NOT wrptrclr AND wrinc));
</td></tr><tr><td>
FTCPE_wrptr1: FTCPE port map (wrptr(1),wrptr_T(1),clk,rst,'0','1');
<br/> wrptr_T(1) <= ((wrptrclr AND wrptr(1))
<br/> OR (wrptr(0) AND NOT wrptrclr AND wrinc));
</td></tr><tr><td>
FTCPE_wrptr2: FTCPE port map (wrptr(2),wrptr_T(2),clk,rst,'0','1');
<br/> wrptr_T(2) <= ((wrptrclr AND wrptr(2))
<br/> OR (wrptr(0) AND NOT wrptrclr AND wrinc AND wrptr(1)));
</td></tr><tr><td>
</td></tr><tr><td>
Register Legend:
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
<br/> LDCP (Q,D,G,CLR,PRE);
</td></tr><tr><td>
</td></tr>
</table>
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