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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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data_out_I(0) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_0)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_0)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_0)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_0)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_0)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_0)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_0)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_0));
<br/> data_out(0) <= data_out_I(0) when data_out_OE(0) = '1' else 'Z';
<br/> data_out_OE(0) <= rd;
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data_out_I(1) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_1)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_1)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_1)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_1)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_1)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_1)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_1)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_1));
<br/> data_out(1) <= data_out_I(1) when data_out_OE(1) = '1' else 'Z';
<br/> data_out_OE(1) <= rd;
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data_out_I(2) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_2)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_2)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_2)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_2)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_2)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_2)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_2)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_2));
<br/> data_out(2) <= data_out_I(2) when data_out_OE(2) = '1' else 'Z';
<br/> data_out_OE(2) <= rd;
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data_out_I(3) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_3)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_3)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_3)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_3)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_3)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_3)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_3)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_3));
<br/> data_out(3) <= data_out_I(3) when data_out_OE(3) = '1' else 'Z';
<br/> data_out_OE(3) <= rd;
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data_out_I(4) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_4)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_4)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_4)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_4)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_4)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_4)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_4)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_4));
<br/> data_out(4) <= data_out_I(4) when data_out_OE(4) = '1' else 'Z';
<br/> data_out_OE(4) <= rd;
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data_out_I(5) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_5)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_5)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_5)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_5)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_5)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_5)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_5)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_5));
<br/> data_out(5) <= data_out_I(5) when data_out_OE(5) = '1' else 'Z';
<br/> data_out_OE(5) <= rd;
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data_out_I(6) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_6)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_6)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_6)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_6)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_6)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_6)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_6)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_6));
<br/> data_out(6) <= data_out_I(6) when data_out_OE(6) = '1' else 'Z';
<br/> data_out_OE(6) <= rd;
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data_out_I(7) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_7)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_7)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_7)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_7)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_7)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_7)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_7)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_7));
<br/> data_out(7) <= data_out_I(7) when data_out_OE(7) = '1' else 'Z';
<br/> data_out_OE(7) <= rd;
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data_out_I(8) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_8)
<br/> OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_8)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_8)
<br/> OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_8)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_8)
<br/> OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_8)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_8)
<br/> OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_8));
<br/> data_out(8) <= data_out_I(8) when data_out_OE(8) = '1' else 'Z';
<br/> data_out_OE(8) <= rd;
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FDCPE_fifo_0_0: FDCPE port map (fifo_0_0,data_in(0),clk,rst,'0',fifo_0_0_CE);
<br/> fifo_0_0_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_1: FDCPE port map (fifo_0_1,data_in(1),clk,rst,'0',fifo_0_1_CE);
<br/> fifo_0_1_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_2: FDCPE port map (fifo_0_2,data_in(2),clk,rst,'0',fifo_0_2_CE);
<br/> fifo_0_2_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_3: FDCPE port map (fifo_0_3,data_in(3),clk,rst,'0',fifo_0_3_CE);
<br/> fifo_0_3_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_0_4: FDCPE port map (fifo_0_4,data_in(4),clk,rst,'0',fifo_0_4_CE);
<br/> fifo_0_4_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_5: FDCPE port map (fifo_0_5,data_in(5),clk,rst,'0',fifo_0_5_CE);
<br/> fifo_0_5_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_6: FDCPE port map (fifo_0_6,data_in(6),clk,rst,'0',fifo_0_6_CE);
<br/> fifo_0_6_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_7: FDCPE port map (fifo_0_7,data_in(7),clk,rst,'0',fifo_0_7_CE);
<br/> fifo_0_7_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_0_8: FDCPE port map (fifo_0_8,data_in(8),clk,rst,'0',fifo_0_8_CE);
<br/> fifo_0_8_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_0: FDCPE port map (fifo_1_0,data_in(0),clk,rst,'0',fifo_1_0_CE);
<br/> fifo_1_0_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_1: FDCPE port map (fifo_1_1,data_in(1),clk,rst,'0',fifo_1_1_CE);
<br/> fifo_1_1_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_2: FDCPE port map (fifo_1_2,data_in(2),clk,rst,'0',fifo_1_2_CE);
<br/> fifo_1_2_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_3: FDCPE port map (fifo_1_3,data_in(3),clk,rst,'0',fifo_1_3_CE);
<br/> fifo_1_3_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_4: FDCPE port map (fifo_1_4,data_in(4),clk,rst,'0',fifo_1_4_CE);
<br/> fifo_1_4_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_5: FDCPE port map (fifo_1_5,data_in(5),clk,rst,'0',fifo_1_5_CE);
<br/> fifo_1_5_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_6: FDCPE port map (fifo_1_6,data_in(6),clk,rst,'0',fifo_1_6_CE);
<br/> fifo_1_6_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_7: FDCPE port map (fifo_1_7,data_in(7),clk,rst,'0',fifo_1_7_CE);
<br/> fifo_1_7_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_1_8: FDCPE port map (fifo_1_8,data_in(8),clk,rst,'0',fifo_1_8_CE);
<br/> fifo_1_8_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_2_0: FDCPE port map (fifo_2_0,data_in(0),clk,rst,'0',fifo_2_0_CE);
<br/> fifo_2_0_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_2_1: FDCPE port map (fifo_2_1,data_in(1),clk,rst,'0',fifo_2_1_CE);
<br/> fifo_2_1_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_2_2: FDCPE port map (fifo_2_2,data_in(2),clk,rst,'0',fifo_2_2_CE);
<br/> fifo_2_2_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_2_3: FDCPE port map (fifo_2_3,data_in(3),clk,rst,'0',fifo_2_3_CE);
<br/> fifo_2_3_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
</td></tr><tr><td>
FDCPE_fifo_2_4: FDCPE port map (fifo_2_4,data_in(4),clk,rst,'0',fifo_2_4_CE);
<br/> fifo_2_4_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
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FDCPE_fifo_2_5: FDCPE port map (fifo_2_5,data_in(5),clk,rst,'0',fifo_2_5_CE);
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