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FDCPE_fifo_4_1: FDCPE port map (fifo_4_1,data_in(1),clk,rst,'0',fifo_4_1_CE);
fifo_4_1_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_2: FDCPE port map (fifo_4_2,data_in(2),clk,rst,'0',fifo_4_2_CE);
fifo_4_2_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_3: FDCPE port map (fifo_4_3,data_in(3),clk,rst,'0',fifo_4_3_CE);
fifo_4_3_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_4: FDCPE port map (fifo_4_4,data_in(4),clk,rst,'0',fifo_4_4_CE);
fifo_4_4_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_5: FDCPE port map (fifo_4_5,data_in(5),clk,rst,'0',fifo_4_5_CE);
fifo_4_5_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_6: FDCPE port map (fifo_4_6,data_in(6),clk,rst,'0',fifo_4_6_CE);
fifo_4_6_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_7: FDCPE port map (fifo_4_7,data_in(7),clk,rst,'0',fifo_4_7_CE);
fifo_4_7_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_4_8: FDCPE port map (fifo_4_8,data_in(8),clk,rst,'0',fifo_4_8_CE);
fifo_4_8_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_0: FDCPE port map (fifo_5_0,data_in(0),clk,rst,'0',fifo_5_0_CE);
fifo_5_0_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_1: FDCPE port map (fifo_5_1,data_in(1),clk,rst,'0',fifo_5_1_CE);
fifo_5_1_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_2: FDCPE port map (fifo_5_2,data_in(2),clk,rst,'0',fifo_5_2_CE);
fifo_5_2_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_3: FDCPE port map (fifo_5_3,data_in(3),clk,rst,'0',fifo_5_3_CE);
fifo_5_3_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_4: FDCPE port map (fifo_5_4,data_in(4),clk,rst,'0',fifo_5_4_CE);
fifo_5_4_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_5: FDCPE port map (fifo_5_5,data_in(5),clk,rst,'0',fifo_5_5_CE);
fifo_5_5_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_6: FDCPE port map (fifo_5_6,data_in(6),clk,rst,'0',fifo_5_6_CE);
fifo_5_6_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_7: FDCPE port map (fifo_5_7,data_in(7),clk,rst,'0',fifo_5_7_CE);
fifo_5_7_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_5_8: FDCPE port map (fifo_5_8,data_in(8),clk,rst,'0',fifo_5_8_CE);
fifo_5_8_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND wrptr(2));
FDCPE_fifo_6_0: FDCPE port map (fifo_6_0,data_in(0),clk,rst,'0',fifo_6_0_CE);
fifo_6_0_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_1: FDCPE port map (fifo_6_1,data_in(1),clk,rst,'0',fifo_6_1_CE);
fifo_6_1_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_2: FDCPE port map (fifo_6_2,data_in(2),clk,rst,'0',fifo_6_2_CE);
fifo_6_2_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_3: FDCPE port map (fifo_6_3,data_in(3),clk,rst,'0',fifo_6_3_CE);
fifo_6_3_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_4: FDCPE port map (fifo_6_4,data_in(4),clk,rst,'0',fifo_6_4_CE);
fifo_6_4_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_5: FDCPE port map (fifo_6_5,data_in(5),clk,rst,'0',fifo_6_5_CE);
fifo_6_5_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_6: FDCPE port map (fifo_6_6,data_in(6),clk,rst,'0',fifo_6_6_CE);
fifo_6_6_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_7: FDCPE port map (fifo_6_7,data_in(7),clk,rst,'0',fifo_6_7_CE);
fifo_6_7_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_6_8: FDCPE port map (fifo_6_8,data_in(8),clk,rst,'0',fifo_6_8_CE);
fifo_6_8_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_0: FDCPE port map (fifo_7_0,data_in(0),clk,rst,'0',fifo_7_0_CE);
fifo_7_0_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_1: FDCPE port map (fifo_7_1,data_in(1),clk,rst,'0',fifo_7_1_CE);
fifo_7_1_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_2: FDCPE port map (fifo_7_2,data_in(2),clk,rst,'0',fifo_7_2_CE);
fifo_7_2_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_3: FDCPE port map (fifo_7_3,data_in(3),clk,rst,'0',fifo_7_3_CE);
fifo_7_3_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_4: FDCPE port map (fifo_7_4,data_in(4),clk,rst,'0',fifo_7_4_CE);
fifo_7_4_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_5: FDCPE port map (fifo_7_5,data_in(5),clk,rst,'0',fifo_7_5_CE);
fifo_7_5_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_6: FDCPE port map (fifo_7_6,data_in(6),clk,rst,'0',fifo_7_6_CE);
fifo_7_6_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_7: FDCPE port map (fifo_7_7,data_in(7),clk,rst,'0',fifo_7_7_CE);
fifo_7_7_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_fifo_7_8: FDCPE port map (fifo_7_8,data_in(8),clk,rst,'0',fifo_7_8_CE);
fifo_7_8_CE <= (wr AND wrptr(0) AND wrptr(1) AND wrptr(2));
FDCPE_rdptr0: FDCPE port map (rdptr(0),rdptr_D(0),clk,rst,'0','1');
rdptr_D(0) <= ((NOT rdptrclr AND rdinc AND NOT rdptr(0))
OR (NOT rdptrclr AND NOT rdinc AND rdptr(0)));
FTCPE_rdptr1: FTCPE port map (rdptr(1),rdptr_T(1),clk,rst,'0','1');
rdptr_T(1) <= ((rdptrclr AND rdptr(1))
OR (NOT rdptrclr AND rdinc AND rdptr(0)));
FTCPE_rdptr2: FTCPE port map (rdptr(2),rdptr_T(2),clk,rst,'0','1');
rdptr_T(2) <= ((rdptr(2) AND rdptrclr)
OR (NOT rdptrclr AND rdinc AND rdptr(1) AND rdptr(0)));
FDCPE_wrptr0: FDCPE port map (wrptr(0),wrptr_D(0),clk,rst,'0','1');
wrptr_D(0) <= ((wrptr(0) AND NOT wrptrclr AND NOT wrinc)
OR (NOT wrptr(0) AND NOT wrptrclr AND wrinc));
FTCPE_wrptr1: FTCPE port map (wrptr(1),wrptr_T(1),clk,rst,'0','1');
wrptr_T(1) <= ((wrptrclr AND wrptr(1))
OR (wrptr(0) AND NOT wrptrclr AND wrinc));
FTCPE_wrptr2: FTCPE port map (wrptr(2),wrptr_T(2),clk,rst,'0','1');
wrptr_T(2) <= ((wrptrclr AND wrptr(2))
OR (wrptr(0) AND NOT wrptrclr AND wrinc AND wrptr(1)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XCR3128XL-6-VQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XCR3128XL-6-VQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 WPU 51 VCC
2 WPU 52 WPU
3 VCC 53 WPU
4 TDI 54 WPU
5 WPU 55 WPU
6 WPU 56 WPU
7 WPU 57 data_out<7>
8 WPU 58 data_out<6>
9 WPU 59 GND
10 WPU 60 data_out<5>
11 PE 61 data_out<4>
12 WPU 62 TCK
13 WPU 63 data_in<8>
14 WPU 64 data_in<7>
15 TMS 65 data_in<6>
16 WPU 66 VCC
17 WPU 67 data_in<5>
18 VCC 68 data_in<4>
19 WPU 69 data_in<3>
20 WPU 70 data_in<2>
21 WPU 71 data_in<1>
22 WPU 72 data_in<0>
23 WPU 73 TDO
24 WPU 74 GND
25 WPU 75 data_out<0>
26 GND 76 data_out<1>
27 WPU 77 data_out<2>
28 WPU 78 data_out<3>
29 WPU 79 rd
30 WPU 80 rdinc
31 WPU 81 rdptrclr
32 WPU 82 VCC
33 WPU 83 rst
34 VCC 84 WPU
35 WPU 85 WPU
36 WPU 86 GND
37 WPU 87 TIE
38 GND 88 TIE
39 VCC 89 TIE
40 data_out<8> 90 clk
41 wr 91 VCC
42 wrinc 92 WPU
43 GND 93 WPU
44 wrptrclr 94 WPU
45 WPU 95 GND
46 WPU 96 WPU
47 WPU 97 WPU
48 WPU 98 WPU
49 WPU 99 WPU
50 WPU 100 WPU
Legend : NC = Not Connected, unbonded pin
PE = Port Enable pin
WPU = Unused with Internal Weak Pull Up
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xcr3*xl-*-*
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : PULLUP
Set Input-Only Termination : FLOAT
Set Universal Control Term Optimization : OFF
Enable Foldback NANDs : OFF
Reserve ISP Pins : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Input Limit : 32
Pterm Limit : 28
</pre>
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