📄 fifo89.rpt
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fifo_5_8 3 FB7_13 28 I/O (b) clk
fifo_4_8 3 FB7_14 27 I/O (b) clk
fifo_4_5 3 FB7_15 (b) (b) clk
fifo_3_5 3 FB7_16 (b) (b) clk
Signals Used by Logic in Function Block
1: data_in<2> 4: wr 6: wrptr<1>
2: data_in<5> 5: wrptr<0> 7: wrptr<2>
3: data_in<8>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
fifo_3_8 ..XXXXX................................. 5
fifo_7_2 X..XXXX................................. 5
fifo_7_5 .X.XXXX................................. 5
fifo_6_5 .X.XXXX................................. 5
fifo_5_5 .X.XXXX................................. 5
fifo_7_8 ..XXXXX................................. 5
fifo_6_8 ..XXXXX................................. 5
fifo_5_8 ..XXXXX................................. 5
fifo_4_8 ..XXXXX................................. 5
fifo_4_5 .X.XXXX................................. 5
fifo_3_5 .X.XXXX................................. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 0/40
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 0/48
Number of function block global clocks used/remaining: 0/2
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
(unused) 0 FB8_1 (b)
(unused) 0 FB8_2 15 TMS/I/O
(unused) 0 FB8_3 16 I/O
(unused) 0 FB8_4 17 I/O
(unused) 0 FB8_5 (b)
(unused) 0 FB8_6 19 I/O
(unused) 0 FB8_7 20 I/O
(unused) 0 FB8_8 (b)
(unused) 0 FB8_9 (b)
(unused) 0 FB8_10 (b)
(unused) 0 FB8_11 21 I/O
(unused) 0 FB8_12 22 I/O
(unused) 0 FB8_13 23 I/O
(unused) 0 FB8_14 24 I/O
(unused) 0 FB8_15 25 I/O
(unused) 0 FB8_16 (b)
******************************* Equations ********************************
********** Mapped Logic **********
data_out_I(0) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_0)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_0)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_0)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_0)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_0)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_0)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_0)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_0));
data_out(0) <= data_out_I(0) when data_out_OE(0) = '1' else 'Z';
data_out_OE(0) <= rd;
data_out_I(1) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_1)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_1)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_1)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_1)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_1)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_1)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_1)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_1));
data_out(1) <= data_out_I(1) when data_out_OE(1) = '1' else 'Z';
data_out_OE(1) <= rd;
data_out_I(2) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_2)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_2)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_2)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_2)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_2)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_2)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_2)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_2));
data_out(2) <= data_out_I(2) when data_out_OE(2) = '1' else 'Z';
data_out_OE(2) <= rd;
data_out_I(3) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_3)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_3)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_3)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_3)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_3)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_3)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_3)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_3));
data_out(3) <= data_out_I(3) when data_out_OE(3) = '1' else 'Z';
data_out_OE(3) <= rd;
data_out_I(4) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_4)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_4)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_4)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_4)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_4)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_4)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_4)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_4));
data_out(4) <= data_out_I(4) when data_out_OE(4) = '1' else 'Z';
data_out_OE(4) <= rd;
data_out_I(5) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_5)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_5)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_5)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_5)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_5)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_5)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_5)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_5));
data_out(5) <= data_out_I(5) when data_out_OE(5) = '1' else 'Z';
data_out_OE(5) <= rd;
data_out_I(6) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_6)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_6)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_6)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_6)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_6)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_6)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_6)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_6));
data_out(6) <= data_out_I(6) when data_out_OE(6) = '1' else 'Z';
data_out_OE(6) <= rd;
data_out_I(7) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_7)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_7)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_7)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_7)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_7)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_7)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_7)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_7));
data_out(7) <= data_out_I(7) when data_out_OE(7) = '1' else 'Z';
data_out_OE(7) <= rd;
data_out_I(8) <= ((rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_7_8)
OR (rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_6_8)
OR (rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_5_8)
OR (rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_4_8)
OR (NOT rdptr(2) AND rdptr(1) AND rdptr(0) AND fifo_3_8)
OR (NOT rdptr(2) AND rdptr(1) AND NOT rdptr(0) AND fifo_2_8)
OR (NOT rdptr(2) AND NOT rdptr(1) AND rdptr(0) AND fifo_1_8)
OR (NOT rdptr(2) AND NOT rdptr(1) AND NOT rdptr(0) AND fifo_0_8));
data_out(8) <= data_out_I(8) when data_out_OE(8) = '1' else 'Z';
data_out_OE(8) <= rd;
FDCPE_fifo_0_0: FDCPE port map (fifo_0_0,data_in(0),clk,rst,'0',fifo_0_0_CE);
fifo_0_0_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_1: FDCPE port map (fifo_0_1,data_in(1),clk,rst,'0',fifo_0_1_CE);
fifo_0_1_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_2: FDCPE port map (fifo_0_2,data_in(2),clk,rst,'0',fifo_0_2_CE);
fifo_0_2_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_3: FDCPE port map (fifo_0_3,data_in(3),clk,rst,'0',fifo_0_3_CE);
fifo_0_3_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_4: FDCPE port map (fifo_0_4,data_in(4),clk,rst,'0',fifo_0_4_CE);
fifo_0_4_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_5: FDCPE port map (fifo_0_5,data_in(5),clk,rst,'0',fifo_0_5_CE);
fifo_0_5_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_6: FDCPE port map (fifo_0_6,data_in(6),clk,rst,'0',fifo_0_6_CE);
fifo_0_6_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_7: FDCPE port map (fifo_0_7,data_in(7),clk,rst,'0',fifo_0_7_CE);
fifo_0_7_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_0_8: FDCPE port map (fifo_0_8,data_in(8),clk,rst,'0',fifo_0_8_CE);
fifo_0_8_CE <= (wr AND NOT wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_0: FDCPE port map (fifo_1_0,data_in(0),clk,rst,'0',fifo_1_0_CE);
fifo_1_0_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_1: FDCPE port map (fifo_1_1,data_in(1),clk,rst,'0',fifo_1_1_CE);
fifo_1_1_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_2: FDCPE port map (fifo_1_2,data_in(2),clk,rst,'0',fifo_1_2_CE);
fifo_1_2_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_3: FDCPE port map (fifo_1_3,data_in(3),clk,rst,'0',fifo_1_3_CE);
fifo_1_3_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_4: FDCPE port map (fifo_1_4,data_in(4),clk,rst,'0',fifo_1_4_CE);
fifo_1_4_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_5: FDCPE port map (fifo_1_5,data_in(5),clk,rst,'0',fifo_1_5_CE);
fifo_1_5_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_6: FDCPE port map (fifo_1_6,data_in(6),clk,rst,'0',fifo_1_6_CE);
fifo_1_6_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_7: FDCPE port map (fifo_1_7,data_in(7),clk,rst,'0',fifo_1_7_CE);
fifo_1_7_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_1_8: FDCPE port map (fifo_1_8,data_in(8),clk,rst,'0',fifo_1_8_CE);
fifo_1_8_CE <= (wr AND wrptr(0) AND NOT wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_0: FDCPE port map (fifo_2_0,data_in(0),clk,rst,'0',fifo_2_0_CE);
fifo_2_0_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_1: FDCPE port map (fifo_2_1,data_in(1),clk,rst,'0',fifo_2_1_CE);
fifo_2_1_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_2: FDCPE port map (fifo_2_2,data_in(2),clk,rst,'0',fifo_2_2_CE);
fifo_2_2_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_3: FDCPE port map (fifo_2_3,data_in(3),clk,rst,'0',fifo_2_3_CE);
fifo_2_3_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_4: FDCPE port map (fifo_2_4,data_in(4),clk,rst,'0',fifo_2_4_CE);
fifo_2_4_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_5: FDCPE port map (fifo_2_5,data_in(5),clk,rst,'0',fifo_2_5_CE);
fifo_2_5_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_6: FDCPE port map (fifo_2_6,data_in(6),clk,rst,'0',fifo_2_6_CE);
fifo_2_6_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_7: FDCPE port map (fifo_2_7,data_in(7),clk,rst,'0',fifo_2_7_CE);
fifo_2_7_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_2_8: FDCPE port map (fifo_2_8,data_in(8),clk,rst,'0',fifo_2_8_CE);
fifo_2_8_CE <= (wr AND NOT wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_0: FDCPE port map (fifo_3_0,data_in(0),clk,rst,'0',fifo_3_0_CE);
fifo_3_0_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_1: FDCPE port map (fifo_3_1,data_in(1),clk,rst,'0',fifo_3_1_CE);
fifo_3_1_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_2: FDCPE port map (fifo_3_2,data_in(2),clk,rst,'0',fifo_3_2_CE);
fifo_3_2_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_3: FDCPE port map (fifo_3_3,data_in(3),clk,rst,'0',fifo_3_3_CE);
fifo_3_3_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_4: FDCPE port map (fifo_3_4,data_in(4),clk,rst,'0',fifo_3_4_CE);
fifo_3_4_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_5: FDCPE port map (fifo_3_5,data_in(5),clk,rst,'0',fifo_3_5_CE);
fifo_3_5_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_6: FDCPE port map (fifo_3_6,data_in(6),clk,rst,'0',fifo_3_6_CE);
fifo_3_6_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_7: FDCPE port map (fifo_3_7,data_in(7),clk,rst,'0',fifo_3_7_CE);
fifo_3_7_CE <= (wr AND wrptr(0) AND wrptr(1) AND NOT wrptr(2));
FDCPE_fifo_3_8: FDCPE port map (fifo_3_8,data_in(8),clk,rst,'0',fifo_3_8_CE);
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