📄 fifo89.rpt
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cpldfit: version J.33 Xilinx Inc.
Fitter Report
Design Name: fifo89 Date: 12- 8-2007, 2:30PM
Device Used: XCR3128XL-6-VQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
87 /128 ( 68%) 206 /384 ( 54%) 121 /320 ( 38%) 78 /128 ( 61%) 26 /80 ( 32%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO GCK
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/16* 5/40 16/48 0/ 9 1/2
FB2 7/16 38/40* 39/48 4/10 1/2
FB3 5/16 38/40* 34/48 4/ 9 1/2
FB4 16/16* 19/40 37/48 1/10 1/2
FB5 16/16* 7/40 30/48 0/10 1/2
FB6 16/16* 7/40 30/48 0/ 9 1/2
FB7 11/16 7/40 20/48 0/10 1/2
FB8 0/16 0/40 0/48 0/ 9 0/2
----- ------- ------- -----
Total 87/128 121/320 206/384 9/76
* - Resource is exhausted
** Local Control Term Resources **
LCT0 LCT1 LCT2 LCT3 LCT4 LCT5 LCT6 LCT7
FB1 ce uct2
FB2 uct4
FB3
FB4 ce
FB5 ce
FB6 ce
FB7 ce
FB8
Legend:
ce - clock enable
clk - clock
oe - output enable
sr - set/reset
uct1 - universal control term clock
uct2 - universal control term output enable
uct3 - universal control term preset
uct4 - universal control term reset
LCT0 - oe and/or sr can be mapped to this local control term
LCT1 - oe and/or sr can be mapped to this local control term
LCT2 - oe and/or sr can be mapped to this local control term
LCT3 - sr can be mapped to this local control term
LCT4 - ce and/or clk and/or sr can be mapped to this local control term
LCT5 - clk and/or sr can be mapped to this local control term
LCT6 - clk and/or oe can be mapped to this local control term
LCT7 - clk can be mapped to this local control term
** Global Control Resources **
GCK UCLK UOE UPST URST
Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
1/4 0/1 1/1 0/1 1/1
GCK - Global Clock
UCLK - Universal Control Term Clock
UOE - Universal Control Term Output Enable
UPST - Universal Control Term Preset
URST - Universal Control Term Reset
Signal 'clk' mapped onto global clock net GCK0.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|-------------------------------------
Input : 16 16 | I/O : 25 76
Output : 9 9 | GCK/I : 1 4
Bidirectional : 0 0 |
GCK : 1 1 |
---- ----
Total 26 26
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 9 Outputs **
Signal Total Total Loc Pin Pin Pin Slew Reg Init
Name Pts Inps No. Type Use Rate State
data_out<0> 9 11 FB2_1 75 I/O O FAST
data_out<1> 9 11 FB2_2 76 I/O O FAST
data_out<2> 9 11 FB2_3 77 I/O O FAST
data_out<3> 9 11 FB2_4 78 I/O O FAST
data_out<4> 9 11 FB3_3 61 I/O O FAST
data_out<5> 9 11 FB3_4 60 I/O O FAST
data_out<6> 9 11 FB3_6 58 I/O O FAST
data_out<7> 9 11 FB3_7 57 I/O O FAST
data_out<8> 9 11 FB4_2 40 I/O O FAST
** 78 Buried Nodes **
Signal Total Total Loc Reg Init
Name Pts Inps State
fifo_7_0 3 5 FB1_1 RESET
fifo_1_0 3 5 FB1_2 RESET
fifo_0_0 2 4 FB1_3 RESET
fifo_0_1 2 4 FB1_4 RESET
fifo_0_2 2 4 FB1_5 RESET
fifo_0_3 2 4 FB1_6 RESET
fifo_0_4 2 4 FB1_7 RESET
fifo_6_0 3 5 FB1_8 RESET
fifo_5_0 3 5 FB1_9 RESET
fifo_4_0 3 5 FB1_10 RESET
fifo_0_5 2 4 FB1_11 RESET
fifo_3_0 3 5 FB1_12 RESET
fifo_0_6 2 4 FB1_13 RESET
fifo_0_7 2 4 FB1_14 RESET
fifo_0_8 2 4 FB1_15 RESET
fifo_2_0 3 5 FB1_16 RESET
rdptr<0> 3 4 FB2_14 RESET
rdptr<1> 3 5 FB2_15 RESET
rdptr<2> 3 6 FB2_16 RESET
wrptr<0> 3 3 FB3_2 RESET
fifo_4_1 3 5 FB4_1 RESET
fifo_6_2 3 5 FB4_3 RESET
fifo_5_2 3 5 FB4_4 RESET
fifo_4_2 3 5 FB4_5 RESET
fifo_3_2 3 5 FB4_6 RESET
fifo_2_2 3 5 FB4_7 RESET
fifo_3_1 3 5 FB4_8 RESET
fifo_2_1 3 5 FB4_9 RESET
fifo_1_1 3 5 FB4_10 RESET
fifo_1_2 3 5 FB4_11 RESET
fifo_7_1 3 5 FB4_12 RESET
fifo_6_1 3 5 FB4_13 RESET
fifo_5_1 3 5 FB4_14 RESET
wrptr<2> 3 5 FB4_15 RESET
wrptr<1> 3 4 FB4_16 RESET
fifo_2_5 3 5 FB5_1 RESET
fifo_1_5 3 5 FB5_2 RESET
fifo_7_4 3 5 FB5_3 RESET
fifo_6_4 3 5 FB5_4 RESET
fifo_5_4 3 5 FB5_5 RESET
Signal Total Total Loc Reg Init
Name Pts Inps State
fifo_4_4 3 5 FB5_6 RESET
fifo_3_4 3 5 FB5_7 RESET
fifo_6_3 3 5 FB5_8 RESET
fifo_5_3 3 5 FB5_9 RESET
fifo_4_3 3 5 FB5_10 RESET
fifo_3_3 3 5 FB5_11 RESET
fifo_2_3 3 5 FB5_12 RESET
fifo_2_4 3 5 FB5_13 RESET
fifo_1_4 3 5 FB5_14 RESET
fifo_7_3 3 5 FB5_15 RESET
fifo_1_3 3 5 FB5_16 RESET
fifo_7_6 3 5 FB6_1 RESET
fifo_1_6 3 5 FB6_2 RESET
fifo_2_8 3 5 FB6_3 RESET
fifo_1_8 3 5 FB6_4 RESET
fifo_7_7 3 5 FB6_5 RESET
fifo_6_7 3 5 FB6_6 RESET
fifo_5_7 3 5 FB6_7 RESET
fifo_6_6 3 5 FB6_8 RESET
fifo_5_6 3 5 FB6_9 RESET
fifo_4_6 3 5 FB6_10 RESET
fifo_4_7 3 5 FB6_11 RESET
fifo_3_6 3 5 FB6_12 RESET
fifo_2_6 3 5 FB6_13 RESET
fifo_3_7 3 5 FB6_14 RESET
fifo_2_7 3 5 FB6_15 RESET
fifo_1_7 3 5 FB6_16 RESET
fifo_3_8 3 5 FB7_1 RESET
fifo_7_2 3 5 FB7_7 RESET
fifo_7_5 3 5 FB7_8 RESET
fifo_6_5 3 5 FB7_9 RESET
fifo_5_5 3 5 FB7_10 RESET
fifo_7_8 3 5 FB7_11 RESET
fifo_6_8 3 5 FB7_12 RESET
fifo_5_8 3 5 FB7_13 RESET
fifo_4_8 3 5 FB7_14 RESET
fifo_4_5 3 5 FB7_15 RESET
fifo_3_5 3 5 FB7_16 RESET
** 17 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
data_in<0> FB1_3 72 I/O I
data_in<1> FB1_4 71 I/O I
data_in<2> FB1_5 70 I/O I
data_in<3> FB1_6 69 I/O I
data_in<4> FB1_7 68 I/O I
data_in<5> FB1_11 67 I/O I
data_in<6> FB1_13 65 I/O I
data_in<7> FB1_14 64 I/O I
data_in<8> FB1_15 63 I/O I
rd FB2_5 79 I/O I
rdinc FB2_6 80 I/O I
rdptrclr FB2_7 81 I/O I
rst FB2_11 83 I/O I
wr FB4_3 41 I/O I
wrinc FB4_4 42 I/O I
wrptrclr FB4_5 44 I/O I
clk 90 GCK/I GCK
Legend:
Pin No. - ~ - User Assigned
PU - Pull Up
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/35
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 16/32
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
fifo_7_0 3 FB1_1 (b) (b) clk
fifo_1_0 3 FB1_2 73 TDO/I/O (b) clk
fifo_0_0 2 FB1_3 72 I/O I clk
fifo_0_1 2 FB1_4 71 I/O I clk
fifo_0_2 2 FB1_5 70 I/O I clk
fifo_0_3 2 FB1_6 69 I/O I clk
fifo_0_4 2 FB1_7 68 I/O I clk
fifo_6_0 3 FB1_8 (b) (b) clk
fifo_5_0 3 FB1_9 (b) (b) clk
fifo_4_0 3 FB1_10 (b) (b) clk
fifo_0_5 2 FB1_11 67 I/O I clk
fifo_3_0 3 FB1_12 (b) (b) clk
fifo_0_6 2 FB1_13 65 I/O I clk
fifo_0_7 2 FB1_14 64 I/O I clk
fifo_0_8 2 FB1_15 63 I/O I clk
fifo_2_0 3 FB1_16 (b) (b) clk
Signals Used by Logic in Function Block
1: data_in<0> 3: wrptr<0> 5: wrptr<2>
2: wr 4: wrptr<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
fifo_7_0 XXXXX................................... 5
fifo_1_0 XXXXX................................... 5
fifo_6_0 XXXXX................................... 5
fifo_5_0 XXXXX................................... 5
fifo_4_0 XXXXX................................... 5
fifo_3_0 XXXXX................................... 5
fifo_2_0 XXXXX................................... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 39/9
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
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