fifo89.clk_rgn
来自「在ISE环境下用VHDL写的8*9FIFO」· CLK_RGN 代码 · 共 13 行
CLK_RGN
13 行
Release 9.1.03i - reportgen J.33Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.Sat Dec 08 16:34:56 2007SUMMARY-------There are 0 clock regions:Clock Reports by Clock Regions------------------------------
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