fifo89.pnx

在ISE环境下用VHDL写的8*9FIFO

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (TTL|LVTTL|LVCMOS2|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part arch="xpla3" device="XCR3128XL" pkg="VQ100" spg="-6"/><pin dir="input" nm="clk" no="90"/><pin dir="input" nm="rdptrclr" no="81"/><pin dir="input" nm="rdinc" no="80"/><pin dir="input" nm="rst" no="83"/><pin dir="input" nm="wr" no="41"/><pin dir="input" nm="wrptrclr" no="44"/><pin dir="input" nm="wrinc" no="42"/><pin dir="input" nm="data_in&lt;0&gt;" no="72"/><pin dir="input" nm="rd" no="79"/><pin dir="input" nm="data_in&lt;1&gt;" no="71"/><pin dir="input" nm="data_in&lt;2&gt;" no="70"/><pin dir="input" nm="data_in&lt;3&gt;" no="69"/><pin dir="input" nm="data_in&lt;4&gt;" no="68"/><pin dir="input" nm="data_in&lt;5&gt;" no="67"/><pin dir="input" nm="data_in&lt;6&gt;" no="65"/><pin dir="input" nm="data_in&lt;7&gt;" no="64"/><pin dir="input" nm="data_in&lt;8&gt;" no="63"/><pin dir="output" nm="data_out&lt;0&gt;" no="75" sr="fast"/><pin dir="output" nm="data_out&lt;1&gt;" no="76" sr="fast"/><pin dir="output" nm="data_out&lt;2&gt;" no="77" sr="fast"/><pin dir="output" nm="data_out&lt;3&gt;" no="78" sr="fast"/><pin dir="output" nm="data_out&lt;4&gt;" no="61" sr="fast"/><pin dir="output" nm="data_out&lt;5&gt;" no="60" sr="fast"/><pin dir="output" nm="data_out&lt;6&gt;" no="58" sr="fast"/><pin dir="output" nm="data_out&lt;7&gt;" no="57" sr="fast"/><pin dir="output" nm="data_out&lt;8&gt;" no="40" sr="fast"/></ibis>