wave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--M1_RD is MAX114:inst11|RD
--operation mode is normal

M1_RD_lut_out = !M1_cnt[1] & !M1_cnt[2] & !M1_cnt[0];
M1_RD = DFFEA(M1_RD_lut_out, CLK, VCC, , M1L82, , );


--M1_B is MAX114:inst11|B
--operation mode is normal

M1_B_lut_out = M1_cnt[1] & M1_cnt[3] & !M1_cnt[2] & !M1_cnt[0];
M1_B = DFFEA(M1_B_lut_out, CLK, VCC, , M1L92, , );


--E1_TEMP is DA5180:inst3|TEMP
--operation mode is normal

E1_TEMP_lut_out = !E1_TEMP;
E1_TEMP = DFFEA(E1_TEMP_lut_out, !K1_CLK, VCC, , E1_cnt[0], , );


--E1_DD[9] is DA5180:inst3|DD[9]
--operation mode is normal

E1_DD[9]_lut_out = N1_TEMP[7] & (N2_TEMP[7] # !R1L1) # !N1_TEMP[7] & N2_TEMP[7] & R1L1;
E1_DD[9]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[9]) # (E1_TEMP & E1_DD[9]_lut_out);
E1_DD[9] = DFFEA(E1_DD[9]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[8] is DA5180:inst3|DD[8]
--operation mode is normal

E1_DD[8]_lut_out = N1_TEMP[6] & (N2_TEMP[6] # !R1L1) # !N1_TEMP[6] & N2_TEMP[6] & R1L1;
E1_DD[8]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[8]) # (E1_TEMP & E1_DD[8]_lut_out);
E1_DD[8] = DFFEA(E1_DD[8]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[7] is DA5180:inst3|DD[7]
--operation mode is normal

E1_DD[7]_lut_out = N1_TEMP[5] & (N2_TEMP[5] # !R1L1) # !N1_TEMP[5] & N2_TEMP[5] & R1L1;
E1_DD[7]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[7]) # (E1_TEMP & E1_DD[7]_lut_out);
E1_DD[7] = DFFEA(E1_DD[7]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[6] is DA5180:inst3|DD[6]
--operation mode is normal

E1_DD[6]_lut_out = N1_TEMP[4] & (N2_TEMP[4] # !R1L1) # !N1_TEMP[4] & N2_TEMP[4] & R1L1;
E1_DD[6]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[6]) # (E1_TEMP & E1_DD[6]_lut_out);
E1_DD[6] = DFFEA(E1_DD[6]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[5] is DA5180:inst3|DD[5]
--operation mode is normal

E1_DD[5]_lut_out = N1_TEMP[3] & (N2_TEMP[3] # !R1L1) # !N1_TEMP[3] & N2_TEMP[3] & R1L1;
E1_DD[5]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[5]) # (E1_TEMP & E1_DD[5]_lut_out);
E1_DD[5] = DFFEA(E1_DD[5]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[4] is DA5180:inst3|DD[4]
--operation mode is normal

E1_DD[4]_lut_out = N1_TEMP[2] & (N2_TEMP[2] # !R1L1) # !N1_TEMP[2] & N2_TEMP[2] & R1L1;
E1_DD[4]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[4]) # (E1_TEMP & E1_DD[4]_lut_out);
E1_DD[4] = DFFEA(E1_DD[4]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[3] is DA5180:inst3|DD[3]
--operation mode is normal

E1_DD[3]_lut_out = N1_TEMP[1] & (N2_TEMP[1] # !R1L1) # !N1_TEMP[1] & N2_TEMP[1] & R1L1;
E1_DD[3]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[3]) # (E1_TEMP & E1_DD[3]_lut_out);
E1_DD[3] = DFFEA(E1_DD[3]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[2] is DA5180:inst3|DD[2]
--operation mode is normal

E1_DD[2]_lut_out = N1_TEMP[0] & (N2_TEMP[0] # !R1L1) # !N1_TEMP[0] & N2_TEMP[0] & R1L1;
E1_DD[2]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[2]) # (E1_TEMP & E1_DD[2]_lut_out);
E1_DD[2] = DFFEA(E1_DD[2]_sload_eqn, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[1] is DA5180:inst3|DD[1]
--operation mode is normal

E1_DD[1]_lut_out = J1_TEMP_Q_1[1] & !E1_TEMP;
E1_DD[1] = DFFEA(E1_DD[1]_lut_out, !K1_CLK, VCC, , !E1_cnt[0], , );


--E1_DD[0] is DA5180:inst3|DD[0]
--operation mode is normal

E1_DD[0]_lut_out = J1_TEMP_Q_1[0] & !E1_TEMP;
E1_DD[0] = DFFEA(E1_DD[0]_lut_out, !K1_CLK, VCC, , !E1_cnt[0], , );


--M1_cnt[1] is MAX114:inst11|cnt[1]
--operation mode is normal

M1_cnt[1]_lut_out = M1_cnt[1] & !M1_cnt[0] # !M1_cnt[1] & M1_cnt[0] & (M1_cnt[2] # INTN);
M1_cnt[1] = DFFEA(M1_cnt[1]_lut_out, CLK, VCC, , , , );


--M1_cnt[2] is MAX114:inst11|cnt[2]
--operation mode is normal

M1_cnt[2]_lut_out = !M1_cnt[2];
M1_cnt[2] = DFFEA(M1_cnt[2]_lut_out, CLK, VCC, , M1L1, , );


--M1_cnt[0] is MAX114:inst11|cnt[0]
--operation mode is normal

M1_cnt[0]_lut_out = M1_cnt[0] & !M1_cnt[1] & !INTN & !M1_cnt[2] # !M1_cnt[0] & (M1_cnt[2] # !INTN # !M1_cnt[1]);
M1_cnt[0] = DFFEA(M1_cnt[0]_lut_out, CLK, VCC, , , , );


--M1L82 is MAX114:inst11|Mux~318
--operation mode is normal

M1L82 = !M1_cnt[2] & !M1_cnt[0];


--M1_cnt[3] is MAX114:inst11|cnt[3]
--operation mode is normal

M1_cnt[3]_lut_out = !M1_cnt[3];
M1_cnt[3] = DFFEA(M1_cnt[3]_lut_out, CLK, VCC, , M1L03, , );


--M1L92 is MAX114:inst11|Mux~319
--operation mode is normal

M1L92 = M1_cnt[1] & !M1_cnt[2] & !M1_cnt[0];


--K1_CLK is FREDEVIDER8:inst8|CLK
--operation mode is normal

K1_CLK_lut_out = !K1_CLK;
K1_CLK = DFFEA(K1_CLK_lut_out, CLK, VCC, , K1L6, , );


--E1_cnt[0] is DA5180:inst3|cnt[0]
--operation mode is normal

E1_cnt[0]_lut_out = !E1_cnt[0];
E1_cnt[0] = DFFEA(E1_cnt[0]_lut_out, !K1_CLK, VCC, , , , );


--N1_TEMP[7] is VOLTAGE_CONV:inst12|TEMP[7]
--operation mode is normal

N1_TEMP[7]_lut_out = N1L51;
N1_TEMP[7] = DFFEA(N1_TEMP[7]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[7] is VOLTAGE_CONV:inst15|TEMP[7]
--operation mode is normal

N2_TEMP[7]_lut_out = N2L51;
N2_TEMP[7] = DFFEA(N2_TEMP[7]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[9] is generator_reg81:inst7|TEMP_Q_1[9]
--operation mode is normal

J1_TEMP_Q_1[9]_lut_out = F1_REG_Q[21];
J1_TEMP_Q_1[9] = DFFEA(J1_TEMP_Q_1[9]_lut_out, K1_CLK, !G1_TMP, , , , );


--G1_RAMTMP0[0] is BUS_1:inst5|RAMTMP0[0]
--operation mode is normal

G1_RAMTMP0[0]_lut_out = A1L94 & (G1L49 # G1_RAMTMP0[0] & Y1_q_a[2]) # !A1L94 & G1_RAMTMP0[0] & Y1_q_a[2];
G1_RAMTMP0[0] = DFFEA(G1_RAMTMP0[0]_lut_out, !CLK, VCC, , G1L92, , );


--F1_TEMP is generator_accB:inst4|TEMP
--operation mode is normal

F1_TEMP_lut_out = !F1_TEMP;
F1_TEMP = DFFEA(F1_TEMP_lut_out, K1_CLK, VCC, , F1L07, , );


--G1_RAMTMP0[1] is BUS_1:inst5|RAMTMP0[1]
--operation mode is normal

G1_RAMTMP0[1]_lut_out = A1L84 & (G1L49 # G1_RAMTMP0[1] & Y1_q_a[2]) # !A1L84 & G1_RAMTMP0[1] & Y1_q_a[2];
G1_RAMTMP0[1] = DFFEA(G1_RAMTMP0[1]_lut_out, !CLK, VCC, , G1L92, , );


--R1L1 is MUX2_3:inst17|Q[9]~64
--operation mode is normal

R1L1 = G1_RAMTMP0[0] & (F1_TEMP # !G1_RAMTMP0[1]);


--N1_TEMP[6] is VOLTAGE_CONV:inst12|TEMP[6]
--operation mode is normal

N1_TEMP[6]_lut_out = N1L31;
N1_TEMP[6] = DFFEA(N1_TEMP[6]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[6] is VOLTAGE_CONV:inst15|TEMP[6]
--operation mode is normal

N2_TEMP[6]_lut_out = N2L31;
N2_TEMP[6] = DFFEA(N2_TEMP[6]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[8] is generator_reg81:inst7|TEMP_Q_1[8]
--operation mode is normal

J1_TEMP_Q_1[8]_lut_out = F1_REG_Q[20];
J1_TEMP_Q_1[8] = DFFEA(J1_TEMP_Q_1[8]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1_TEMP[5] is VOLTAGE_CONV:inst12|TEMP[5]
--operation mode is normal

N1_TEMP[5]_lut_out = N1L11;
N1_TEMP[5] = DFFEA(N1_TEMP[5]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[5] is VOLTAGE_CONV:inst15|TEMP[5]
--operation mode is normal

N2_TEMP[5]_lut_out = N2L11;
N2_TEMP[5] = DFFEA(N2_TEMP[5]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[7] is generator_reg81:inst7|TEMP_Q_1[7]
--operation mode is normal

J1_TEMP_Q_1[7]_lut_out = F1_REG_Q[19];
J1_TEMP_Q_1[7] = DFFEA(J1_TEMP_Q_1[7]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1_TEMP[4] is VOLTAGE_CONV:inst12|TEMP[4]
--operation mode is normal

N1_TEMP[4]_lut_out = N1L9;
N1_TEMP[4] = DFFEA(N1_TEMP[4]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[4] is VOLTAGE_CONV:inst15|TEMP[4]
--operation mode is normal

N2_TEMP[4]_lut_out = N2L9;
N2_TEMP[4] = DFFEA(N2_TEMP[4]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[6] is generator_reg81:inst7|TEMP_Q_1[6]
--operation mode is normal

J1_TEMP_Q_1[6]_lut_out = F1_REG_Q[18];
J1_TEMP_Q_1[6] = DFFEA(J1_TEMP_Q_1[6]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1_TEMP[3] is VOLTAGE_CONV:inst12|TEMP[3]
--operation mode is normal

N1_TEMP[3]_lut_out = N1L7;
N1_TEMP[3] = DFFEA(N1_TEMP[3]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[3] is VOLTAGE_CONV:inst15|TEMP[3]
--operation mode is normal

N2_TEMP[3]_lut_out = N2L7;
N2_TEMP[3] = DFFEA(N2_TEMP[3]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[5] is generator_reg81:inst7|TEMP_Q_1[5]
--operation mode is normal

J1_TEMP_Q_1[5]_lut_out = F1_REG_Q[17];
J1_TEMP_Q_1[5] = DFFEA(J1_TEMP_Q_1[5]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1_TEMP[2] is VOLTAGE_CONV:inst12|TEMP[2]
--operation mode is normal

N1_TEMP[2]_lut_out = N1L5;
N1_TEMP[2] = DFFEA(N1_TEMP[2]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[2] is VOLTAGE_CONV:inst15|TEMP[2]
--operation mode is normal

N2_TEMP[2]_lut_out = N2L5;
N2_TEMP[2] = DFFEA(N2_TEMP[2]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[4] is generator_reg81:inst7|TEMP_Q_1[4]
--operation mode is normal

J1_TEMP_Q_1[4]_lut_out = F1_REG_Q[16];
J1_TEMP_Q_1[4] = DFFEA(J1_TEMP_Q_1[4]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1_TEMP[1] is VOLTAGE_CONV:inst12|TEMP[1]
--operation mode is normal

N1_TEMP[1]_lut_out = N1L3;
N1_TEMP[1] = DFFEA(N1_TEMP[1]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );


--N2_TEMP[1] is VOLTAGE_CONV:inst15|TEMP[1]
--operation mode is normal

N2_TEMP[1]_lut_out = N2L3;
N2_TEMP[1] = DFFEA(N2_TEMP[1]_lut_out, !P1_CLK, !U1L6, , !N2L03, , );


--J1_TEMP_Q_1[3] is generator_reg81:inst7|TEMP_Q_1[3]
--operation mode is normal

J1_TEMP_Q_1[3]_lut_out = F1_REG_Q[15];
J1_TEMP_Q_1[3] = DFFEA(J1_TEMP_Q_1[3]_lut_out, K1_CLK, !G1_TMP, , , , );


--N1_TEMP[0] is VOLTAGE_CONV:inst12|TEMP[0]
--operation mode is normal

N1_TEMP[0]_lut_out = N1L1;
N1_TEMP[0] = DFFEA(N1_TEMP[0]_lut_out, !P1_CLK, !U1L6, , !N1L03, , );