da5180.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DA5180 IS
    PORT(CLK: IN STD_LOGIC;
         DAIN1,DAIN2 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
         DAOUT:OUT STD_LOGIC_VECTOR(9 downto 0);
         DACLK: OUT STD_LOGIC;
         DACS,DAEN: OUT STD_LOGIC);
END DA5180;
ARCHITECTURE ART OF DA5180 IS
SIGNAL DD: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL TEMP : STD_LOGIC;
BEGIN
DACS<='0';
DAEN<='1';
PROCESS(CLK)
	variable cnt : integer range 0 to 3 := 0;
BEGIN
IF CLK 'EVENT AND CLK='0' THEN
    CASE CNT IS
    WHEN 0=>
        DD<=DAIN1;
    WHEN 1=>
        TEMP<='0';
    WHEN 2=>
        DD<=DAIN2; 
    WHEN 3=>
        TEMP<='1';
    WHEN OTHERS=>
        NULL;
    END CASE;
    CNT :=CNT + 1;
END IF;
END PROCESS;
DACLK<=TEMP;
DAOUT<=DD;
END ART;