wave.map.summary

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

Flow Status : Successful - Fri Sep 02 10:36:25 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : WAVE
Top-level Entity Name : WAVE
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Production
Total logic elements : 540
Total pins : 46
Total memory bits : 34,816
Total PLLs : 0